all: add HiFive1 rev B board with RISC-V architecture

This page has been a big help in adding support for this new chip:
https://wiki.osdev.org/HiFive-1_Bare_Bones

src/device/riscv/riscv.go

@@ -0,0 +1,10 @@
+package riscv
+
+// Run the given assembly code. The code will be marked as having side effects,
+// as it doesn't produce output and thus would normally be eliminated by the
+// optimizer.
+func Asm(asm string)
+
+// ReadRegister returns the contents of the specified register. The register
+// must be a processor register, reachable with the "mov" instruction.
+func ReadRegister(name string) uintptr

src/device/riscv/start.S

@@ -0,0 +1,13 @@
+.section .init
+.global _start
+.type _start,@function
+
+_start:
+    // Workaround for missing support of the la pseudo-instruction in Clang 8:
+    // https://reviews.llvm.org/D55325
+    lui sp,      %hi(_stack_top)
+    addi sp, sp, %lo(_stack_top)
+    // see https://gnu-mcu-eclipse.github.io/arch/riscv/programmer/#the-gp-global-pointer-register
+    lui gp,      %hi(__global_pointer$)
+    addi gp, gp, %lo(__global_pointer$)
+    call main