mirror of
https://github.com/tinygo-org/tinygo.git
synced 2026-08-05 03:27:48 +00:00
all: add HiFive1 rev B board with RISC-V architecture
This page has been a big help in adding support for this new chip: https://wiki.osdev.org/HiFive-1_Bare_Bones
This commit is contained in:
committed by
Ron Evans
parent
f0eb4eef5a
commit
ffa38b183b
@@ -0,0 +1,10 @@
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package riscv
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// Run the given assembly code. The code will be marked as having side effects,
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// as it doesn't produce output and thus would normally be eliminated by the
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// optimizer.
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func Asm(asm string)
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// ReadRegister returns the contents of the specified register. The register
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// must be a processor register, reachable with the "mov" instruction.
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func ReadRegister(name string) uintptr
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@@ -0,0 +1,13 @@
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.section .init
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.global _start
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.type _start,@function
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_start:
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// Workaround for missing support of the la pseudo-instruction in Clang 8:
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// https://reviews.llvm.org/D55325
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lui sp, %hi(_stack_top)
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addi sp, sp, %lo(_stack_top)
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// see https://gnu-mcu-eclipse.github.io/arch/riscv/programmer/#the-gp-global-pointer-register
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lui gp, %hi(__global_pointer$)
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addi gp, gp, %lo(__global_pointer$)
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call main
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@@ -0,0 +1,38 @@
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// +build hifive1b
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package machine
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const (
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P00 Pin = 0
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P01 Pin = 1
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P02 Pin = 2
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P03 Pin = 3
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P04 Pin = 4
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P05 Pin = 5
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P06 Pin = 6
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P07 Pin = 7
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P08 Pin = 8
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P09 Pin = 9
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P10 Pin = 10
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P11 Pin = 11
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P12 Pin = 12
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P13 Pin = 13
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P14 Pin = 14
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P15 Pin = 15
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P16 Pin = 16
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P17 Pin = 17
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P18 Pin = 18
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P19 Pin = 19
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P20 Pin = 20
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P21 Pin = 21
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P22 Pin = 22
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P23 Pin = 23
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P24 Pin = 24
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P25 Pin = 25
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P26 Pin = 26
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P27 Pin = 27
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P28 Pin = 28
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P29 Pin = 29
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P30 Pin = 30
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P31 Pin = 31
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)
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@@ -0,0 +1,19 @@
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// +build hifive1b
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package machine
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const (
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LED = LED1
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LED1 = LED_RED
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LED2 = LED_GREEN
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LED3 = LED_BLUE
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LED_RED = P22
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LED_GREEN = P19
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LED_BLUE = P21
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)
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const (
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// TODO: figure out the pin numbers for these.
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UART_TX_PIN = NoPin
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UART_RX_PIN = NoPin
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)
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+1
-1
@@ -1,4 +1,4 @@
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// +build !stm32f4disco
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// +build !stm32f4disco,!hifive1b
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package machine
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@@ -0,0 +1,54 @@
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// +build fe310
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package machine
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import (
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"device/sifive"
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)
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type PinMode uint8
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const (
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PinInput PinMode = iota
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PinOutput
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)
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// Configure this pin with the given configuration.
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func (p Pin) Configure(config PinConfig) {
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sifive.GPIO0.INPUT_EN.SetBits(1 << uint8(p))
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if config.Mode == PinOutput {
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sifive.GPIO0.OUTPUT_EN.SetBits(1 << uint8(p))
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}
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}
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// Set the pin to high or low.
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func (p Pin) Set(high bool) {
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if high {
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sifive.GPIO0.PORT.SetBits(1 << uint8(p))
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} else {
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sifive.GPIO0.PORT.ClearBits(1 << uint8(p))
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}
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}
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type UART struct {
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Bus *sifive.UART_Type
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Buffer *RingBuffer
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}
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var (
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UART0 = UART{Bus: sifive.UART0, Buffer: NewRingBuffer()}
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)
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func (uart UART) Configure(config UARTConfig) {
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// Assuming a 16Mhz Crystal (which is Y1 on the HiFive1), the divisor for a
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// 115200 baud rate is 138.
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sifive.UART0.DIV.Set(138)
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sifive.UART0.TXCTRL.Set(sifive.UART_TXCTRL_ENABLE)
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}
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func (uart UART) WriteByte(c byte) {
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for sifive.UART0.TXDATA.Get()&sifive.UART_TXDATA_FULL != 0 {
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}
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sifive.UART0.TXDATA.Set(uint32(c))
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}
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@@ -1,4 +1,4 @@
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// +build !avr,!nrf,!sam,!stm32
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// +build !avr,!nrf,!sam,!sifive,!stm32
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package machine
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+1
-1
@@ -1,4 +1,4 @@
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// +build !stm32f407,!avr
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// +build !stm32f407,!avr,!hifive1b
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package machine
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+1
-1
@@ -1,4 +1,4 @@
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// +build avr nrf sam stm32
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// +build avr nrf sam sifive stm32
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package machine
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@@ -1,4 +1,4 @@
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// +build avr cortexm wasm
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// +build avr cortexm tinygo.riscv wasm
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package os
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+1
-1
@@ -1,4 +1,4 @@
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// +build darwin linux,!avr,!cortexm
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// +build darwin linux,!avr,!cortexm,!tinygo.riscv
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package os
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@@ -1,4 +1,4 @@
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// +build arm,!avr,!cortexm
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// +build arm,!avr,!cortexm,!tinygo.riscv
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package runtime
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+1
-16
@@ -2,26 +2,11 @@
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package runtime
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import (
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"unsafe"
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)
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const GOARCH = "avr"
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const GOARCH = "arm" // avr pretends to be arm
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// The bitness of the CPU (e.g. 8, 32, 64).
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const TargetBits = 8
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//go:extern _heap_start
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var heapStartSymbol unsafe.Pointer
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//go:extern _heap_end
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var heapEndSymbol unsafe.Pointer
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var (
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heapStart = uintptr(unsafe.Pointer(&heapStartSymbol))
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heapEnd = uintptr(unsafe.Pointer(&heapEndSymbol))
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)
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// Align on a word boundary.
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func align(ptr uintptr) uintptr {
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// No alignment necessary on the AVR.
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@@ -3,8 +3,6 @@
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package runtime
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import (
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"unsafe"
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"device/arm"
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)
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@@ -13,29 +11,6 @@ const GOARCH = "arm"
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// The bitness of the CPU (e.g. 8, 32, 64).
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const TargetBits = 32
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//go:extern _heap_start
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var heapStartSymbol unsafe.Pointer
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//go:extern _heap_end
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var heapEndSymbol unsafe.Pointer
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//go:extern _globals_start
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var globalsStartSymbol unsafe.Pointer
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//go:extern _globals_end
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var globalsEndSymbol unsafe.Pointer
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//go:extern _stack_top
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var stackTopSymbol unsafe.Pointer
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var (
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heapStart = uintptr(unsafe.Pointer(&heapStartSymbol))
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heapEnd = uintptr(unsafe.Pointer(&heapEndSymbol))
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globalsStart = uintptr(unsafe.Pointer(&globalsStartSymbol))
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globalsEnd = uintptr(unsafe.Pointer(&globalsEndSymbol))
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stackTop = uintptr(unsafe.Pointer(&stackTopSymbol))
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)
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// Align on word boundary.
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func align(ptr uintptr) uintptr {
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return (ptr + 3) &^ 3
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@@ -0,0 +1,19 @@
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// +build tinygo.riscv
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package runtime
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import "device/riscv"
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const GOARCH = "arm" // riscv pretends to be arm
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// The bitness of the CPU (e.g. 8, 32, 64).
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const TargetBits = 32
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// Align on word boundary.
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func align(ptr uintptr) uintptr {
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return (ptr + 3) &^ 3
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}
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func getCurrentStackPointer() uintptr {
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return riscv.ReadRegister("sp")
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}
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@@ -0,0 +1,30 @@
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// +build avr cortexm tinygo.riscv
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package runtime
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import (
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"unsafe"
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)
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//go:extern _heap_start
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var heapStartSymbol unsafe.Pointer
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//go:extern _heap_end
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var heapEndSymbol unsafe.Pointer
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//go:extern _globals_start
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var globalsStartSymbol unsafe.Pointer
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//go:extern _globals_end
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var globalsEndSymbol unsafe.Pointer
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//go:extern _stack_top
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var stackTopSymbol unsafe.Pointer
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var (
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heapStart = uintptr(unsafe.Pointer(&heapStartSymbol))
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heapEnd = uintptr(unsafe.Pointer(&heapEndSymbol))
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globalsStart = uintptr(unsafe.Pointer(&globalsStartSymbol))
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globalsEnd = uintptr(unsafe.Pointer(&globalsEndSymbol))
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stackTop = uintptr(unsafe.Pointer(&stackTopSymbol))
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)
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@@ -1,5 +1,5 @@
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// +build gc.conservative
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// +build cortexm
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// +build cortexm tinygo.riscv
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package runtime
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@@ -1,5 +1,5 @@
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// +build gc.conservative
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// +build !cortexm
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// +build !cortexm,!tinygo.riscv
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package runtime
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@@ -1,5 +1,5 @@
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// +build gc.conservative
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// +build !cortexm
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// +build !cortexm,!tinygo.riscv
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package runtime
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@@ -1,5 +1,5 @@
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// +build gc.conservative
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// +build cortexm
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// +build cortexm tinygo.riscv
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package runtime
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@@ -0,0 +1,115 @@
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// +build fe310
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// This file implements target-specific things for the FE310 chip as used in the
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// HiFive1.
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package runtime
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import (
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"machine"
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"unsafe"
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"device/riscv"
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"device/sifive"
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)
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type timeUnit int64
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const tickMicros = 32768 // RTC runs at 32.768kHz
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//go:extern _sbss
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var _sbss unsafe.Pointer
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//go:extern _ebss
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var _ebss unsafe.Pointer
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//go:extern _sdata
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var _sdata unsafe.Pointer
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//go:extern _sidata
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var _sidata unsafe.Pointer
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//go:extern _edata
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var _edata unsafe.Pointer
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//go:export main
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func main() {
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preinit()
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initAll()
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callMain()
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abort()
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}
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func init() {
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pric_init()
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machine.UART0.Configure(machine.UARTConfig{})
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}
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func pric_init() {
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// Make sure the HFROSC is on
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sifive.PRIC.HFROSCCFG.SetBits(sifive.PRIC_HFROSCCFG_ENABLE)
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// Run off 16 MHz Crystal for accuracy.
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sifive.PRIC.PLLCFG.SetBits(sifive.PRIC_PLLCFG_REFSEL | sifive.PRIC_PLLCFG_BYPASS)
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sifive.PRIC.PLLCFG.SetBits(sifive.PRIC_PLLCFG_SEL)
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// Turn off HFROSC to save power
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sifive.PRIC.HFROSCCFG.ClearBits(sifive.PRIC_HFROSCCFG_ENABLE)
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// Enable the RTC.
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sifive.RTC.CONFIG.Set(sifive.RTC_CONFIG_ENALWAYS)
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}
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func preinit() {
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// Initialize .bss: zero-initialized global variables.
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ptr := uintptr(unsafe.Pointer(&_sbss))
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for ptr != uintptr(unsafe.Pointer(&_ebss)) {
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*(*uint32)(unsafe.Pointer(ptr)) = 0
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ptr += 4
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}
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// Initialize .data: global variables initialized from flash.
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src := uintptr(unsafe.Pointer(&_sidata))
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dst := uintptr(unsafe.Pointer(&_sdata))
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for dst != uintptr(unsafe.Pointer(&_edata)) {
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*(*uint32)(unsafe.Pointer(dst)) = *(*uint32)(unsafe.Pointer(src))
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dst += 4
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src += 4
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}
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}
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func putchar(c byte) {
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machine.UART0.WriteByte(c)
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}
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func ticks() timeUnit {
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// Combining the low bits and the high bits yields a time span of over 270
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// years without counter rollover.
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highBits := sifive.RTC.HI.Get()
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for {
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lowBits := sifive.RTC.LO.Get()
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newHighBits := sifive.RTC.HI.Get()
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if newHighBits == highBits {
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// High bits stayed the same.
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return timeUnit(lowBits) | (timeUnit(highBits) << 32)
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}
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// Retry, because there was a rollover in the low bits (happening every
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// 1.5 days).
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highBits = newHighBits
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}
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}
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const asyncScheduler = false
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func sleepTicks(d timeUnit) {
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target := ticks() + d
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for ticks() < target {
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}
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}
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func abort() {
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// lock up forever
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for {
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riscv.Asm("wfi")
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}
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}
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@@ -0,0 +1,19 @@
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// +build tinygo.riscv
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package runtime
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import "unsafe"
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// Implement memset for LLVM.
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//go:export memset
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func libc_memset(ptr unsafe.Pointer, c byte, size uintptr) {
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for i := uintptr(0); i < size; i++ {
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*(*byte)(unsafe.Pointer(uintptr(ptr) + i)) = c
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}
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}
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// Implement memmove for LLVM.
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//go:export memmove
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func libc_memmove(dst, src unsafe.Pointer, size uintptr) {
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memmove(dst, src, size)
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}
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@@ -1,4 +1,4 @@
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// +build darwin linux,!avr,!cortexm
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// +build darwin linux,!avr,!cortexm,!tinygo.riscv
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package runtime
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Reference in New Issue
Block a user