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mimxrt1062: move device-specific files to "device/nxp" package
This commit is contained in:
ardnew
Ron Evans
@@ -3,35 +3,12 @@
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package runtime
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import (
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"device/arm"
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"device/nxp"
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"runtime/volatile"
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"unsafe"
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)
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type MPU_Type struct {
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TYPE volatile.Register32 // 0x000 (R/ ) - MPU Type Register
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CTRL volatile.Register32 // 0x004 (R/W) - MPU Control Register
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RNR volatile.Register32 // 0x008 (R/W) - MPU Region RNRber Register
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RBAR volatile.Register32 // 0x00C (R/W) - MPU Region Base Address Register
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RASR volatile.Register32 // 0x010 (R/W) - MPU Region Attribute and Size Register
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RBAR_A1 volatile.Register32 // 0x014 (R/W) - MPU Alias 1 Region Base Address Register
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RASR_A1 volatile.Register32 // 0x018 (R/W) - MPU Alias 1 Region Attribute and Size Register
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RBAR_A2 volatile.Register32 // 0x01C (R/W) - MPU Alias 2 Region Base Address Register
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RASR_A2 volatile.Register32 // 0x020 (R/W) - MPU Alias 2 Region Attribute and Size Register
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RBAR_A3 volatile.Register32 // 0x024 (R/W) - MPU Alias 3 Region Base Address Register
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RASR_A3 volatile.Register32 // 0x028 (R/W) - MPU Alias 3 Region Attribute and Size Register
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}
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var MPU = (*MPU_Type)(unsafe.Pointer(uintptr(0xe000ed90)))
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func initCache() {
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MPU.initialize()
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}
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func (mpu *MPU_Type) initialize() {
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mpu.enable(false)
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nxp.MPU.Enable(false)
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// -------------------------------------------------------- OVERLAY REGIONS --
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@@ -40,310 +17,45 @@ func (mpu *MPU_Type) initialize() {
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// [0] Default {OVERLAY}:
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// 4 GiB, -access, @device, -exec, -share, -cache, -buffer, -subregion
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mpu.setRBAR(0, 0x00000000)
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mpu.setRASR(rs4GB, apNone, exDevice, false, false, false, false, false)
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nxp.MPU.SetRBAR(0, 0x00000000)
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nxp.MPU.SetRASR(nxp.RGNSZ_4GB, nxp.PERM_NONE, nxp.EXTN_DEVICE, false, false, false, false, false)
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// [1] Peripherals {OVERLAY}:
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// 64 MiB, +ACCESS, @device, +EXEC, -share, -cache, -buffer, -subregion
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mpu.setRBAR(1, 0x40000000)
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mpu.setRASR(rs64MB, apFull, exDevice, true, false, false, false, false)
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nxp.MPU.SetRBAR(1, 0x40000000)
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nxp.MPU.SetRASR(nxp.RGNSZ_64MB, nxp.PERM_FULL, nxp.EXTN_DEVICE, true, false, false, false, false)
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// [2] RAM {OVERLAY}:
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// 1 GiB, +ACCESS, @device, +EXEC, -share, -cache, -buffer, -subregion
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mpu.setRBAR(2, 0x00000000)
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mpu.setRASR(rs1GB, apFull, exDevice, true, false, false, false, false)
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nxp.MPU.SetRBAR(2, 0x00000000)
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nxp.MPU.SetRASR(nxp.RGNSZ_1GB, nxp.PERM_FULL, nxp.EXTN_DEVICE, true, false, false, false, false)
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// ----------------------------------------------------- PERIPHERAL REGIONS --
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// [3] ITCM:
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// 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, -cache, -buffer, -subregion
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mpu.setRBAR(3, 0x00000000)
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mpu.setRASR(rs512KB, apFull, exNormal, true, false, false, false, false)
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nxp.MPU.SetRBAR(3, 0x00000000)
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nxp.MPU.SetRASR(nxp.RGNSZ_512KB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, false, false, false)
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// [4] DTCM:
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// 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, -cache, -buffer, -subregion
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mpu.setRBAR(4, 0x20000000)
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mpu.setRASR(rs512KB, apFull, exNormal, true, false, false, false, false)
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nxp.MPU.SetRBAR(4, 0x20000000)
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nxp.MPU.SetRASR(nxp.RGNSZ_512KB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, false, false, false)
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// [5] RAM (AXI):
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// 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion
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mpu.setRBAR(5, 0x20200000)
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mpu.setRASR(rs512KB, apFull, exNormal, true, false, true, true, false)
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nxp.MPU.SetRBAR(5, 0x20200000)
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nxp.MPU.SetRASR(nxp.RGNSZ_512KB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, true, true, false)
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// [6] FlexSPI:
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// 512 MiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion
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mpu.setRBAR(6, 0x70000000)
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mpu.setRASR(rs512MB, apFull, exNormal, true, false, true, true, false)
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nxp.MPU.SetRBAR(6, 0x70000000)
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nxp.MPU.SetRASR(nxp.RGNSZ_512MB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, true, true, false)
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// [7] QSPI flash:
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// 2 MiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion
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mpu.setRBAR(7, 0x60000000)
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mpu.setRASR(rs2MB, apFull, exNormal, true, false, true, true, false)
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nxp.MPU.SetRBAR(7, 0x60000000)
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nxp.MPU.SetRASR(nxp.RGNSZ_2MB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, true, true, false)
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mpu.enable(true)
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}
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// MPU Type Register Definitions
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const (
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MPU_TYPE_IREGION_Pos = 16 // MPU TYPE: IREGION Position
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MPU_TYPE_IREGION_Msk = 0xFF << MPU_TYPE_IREGION_Pos // MPU TYPE: IREGION Mask
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MPU_TYPE_DREGION_Pos = 8 // MPU TYPE: DREGION Position
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MPU_TYPE_DREGION_Msk = 0xFF << MPU_TYPE_DREGION_Pos // MPU TYPE: DREGION Mask
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MPU_TYPE_SEPARATE_Pos = 0 // MPU TYPE: SEPARATE Position
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MPU_TYPE_SEPARATE_Msk = 1 // MPU TYPE: SEPARATE Mask
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)
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// MPU Control Register Definitions
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const (
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MPU_CTRL_PRIVDEFENA_Pos = 2 // MPU CTRL: PRIVDEFENA Position
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MPU_CTRL_PRIVDEFENA_Msk = 1 << MPU_CTRL_PRIVDEFENA_Pos // MPU CTRL: PRIVDEFENA Mask
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MPU_CTRL_HFNMIENA_Pos = 1 // MPU CTRL: HFNMIENA Position
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MPU_CTRL_HFNMIENA_Msk = 1 << MPU_CTRL_HFNMIENA_Pos // MPU CTRL: HFNMIENA Mask
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MPU_CTRL_ENABLE_Pos = 0 // MPU CTRL: ENABLE Position
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MPU_CTRL_ENABLE_Msk = 1 // MPU CTRL: ENABLE Mask
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)
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// MPU Region Number Register Definitions
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const (
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MPU_RNR_REGION_Pos = 0 // MPU RNR: REGION Position
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MPU_RNR_REGION_Msk = 0xFF // MPU RNR: REGION Mask
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)
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// MPU Region Base Address Register Definitions
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const (
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MPU_RBAR_ADDR_Pos = 5 // MPU RBAR: ADDR Position
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MPU_RBAR_ADDR_Msk = 0x7FFFFFF << MPU_RBAR_ADDR_Pos // MPU RBAR: ADDR Mask
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MPU_RBAR_VALID_Pos = 4 // MPU RBAR: VALID Position
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MPU_RBAR_VALID_Msk = 1 << MPU_RBAR_VALID_Pos // MPU RBAR: VALID Mask
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MPU_RBAR_REGION_Pos = 0 // MPU RBAR: REGION Position
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MPU_RBAR_REGION_Msk = 0xF // MPU RBAR: REGION Mask
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)
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// MPU Region Attribute and Size Register Definitions
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const (
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MPU_RASR_ATTRS_Pos = 16 // MPU RASR: MPU Region Attribute field Position
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MPU_RASR_ATTRS_Msk = 0xFFFF << MPU_RASR_ATTRS_Pos // MPU RASR: MPU Region Attribute field Mask
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MPU_RASR_XN_Pos = 28 // MPU RASR: ATTRS.XN Position
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MPU_RASR_XN_Msk = 1 << MPU_RASR_XN_Pos // MPU RASR: ATTRS.XN Mask
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MPU_RASR_AP_Pos = 24 // MPU RASR: ATTRS.AP Position
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MPU_RASR_AP_Msk = 0x7 << MPU_RASR_AP_Pos // MPU RASR: ATTRS.AP Mask
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MPU_RASR_TEX_Pos = 19 // MPU RASR: ATTRS.TEX Position
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MPU_RASR_TEX_Msk = 0x7 << MPU_RASR_TEX_Pos // MPU RASR: ATTRS.TEX Mask
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MPU_RASR_S_Pos = 18 // MPU RASR: ATTRS.S Position
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MPU_RASR_S_Msk = 1 << MPU_RASR_S_Pos // MPU RASR: ATTRS.S Mask
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MPU_RASR_C_Pos = 17 // MPU RASR: ATTRS.C Position
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MPU_RASR_C_Msk = 1 << MPU_RASR_C_Pos // MPU RASR: ATTRS.C Mask
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MPU_RASR_B_Pos = 16 // MPU RASR: ATTRS.B Position
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MPU_RASR_B_Msk = 1 << MPU_RASR_B_Pos // MPU RASR: ATTRS.B Mask
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MPU_RASR_SRD_Pos = 8 // MPU RASR: Sub-Region Disable Position
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MPU_RASR_SRD_Msk = 0xFF << MPU_RASR_SRD_Pos // MPU RASR: Sub-Region Disable Mask
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MPU_RASR_SIZE_Pos = 1 // MPU RASR: Region Size Field Position
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MPU_RASR_SIZE_Msk = 0x1F << MPU_RASR_SIZE_Pos // MPU RASR: Region Size Field Mask
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MPU_RASR_ENABLE_Pos = 0 // MPU RASR: Region enable bit Position
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MPU_RASR_ENABLE_Msk = 1 // MPU RASR: Region enable bit Disable Mask
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)
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const (
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SCB_DCISW_WAY_Pos = 30 // SCB DCISW: Way Position
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SCB_DCISW_WAY_Msk = 3 << SCB_DCISW_WAY_Pos // SCB DCISW: Way Mask
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SCB_DCISW_SET_Pos = 5 // SCB DCISW: Set Position
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SCB_DCISW_SET_Msk = 0x1FF << SCB_DCISW_SET_Pos // SCB DCISW: Set Mask
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)
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const (
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SCB_DCCISW_WAY_Pos = 30 // SCB DCCISW: Way Position
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SCB_DCCISW_WAY_Msk = 3 << SCB_DCCISW_WAY_Pos // SCB DCCISW: Way Mask
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SCB_DCCISW_SET_Pos = 5 // SCB DCCISW: Set Position
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SCB_DCCISW_SET_Msk = 0x1FF << SCB_DCCISW_SET_Pos // SCB DCCISW: Set Mask
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)
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type regionSize uint32
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const (
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rs32B regionSize = 0x04 // MPU Region Size 32 Bytes
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rs64B regionSize = 0x05 // MPU Region Size 64 Bytes
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rs128B regionSize = 0x06 // MPU Region Size 128 Bytes
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rs256B regionSize = 0x07 // MPU Region Size 256 Bytes
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rs512B regionSize = 0x08 // MPU Region Size 512 Bytes
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rs1KB regionSize = 0x09 // MPU Region Size 1 KByte
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rs2KB regionSize = 0x0A // MPU Region Size 2 KBytes
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rs4KB regionSize = 0x0B // MPU Region Size 4 KBytes
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rs8KB regionSize = 0x0C // MPU Region Size 8 KBytes
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rs16KB regionSize = 0x0D // MPU Region Size 16 KBytes
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rs32KB regionSize = 0x0E // MPU Region Size 32 KBytes
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rs64KB regionSize = 0x0F // MPU Region Size 64 KBytes
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rs128KB regionSize = 0x10 // MPU Region Size 128 KBytes
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rs256KB regionSize = 0x11 // MPU Region Size 256 KBytes
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rs512KB regionSize = 0x12 // MPU Region Size 512 KBytes
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rs1MB regionSize = 0x13 // MPU Region Size 1 MByte
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rs2MB regionSize = 0x14 // MPU Region Size 2 MBytes
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rs4MB regionSize = 0x15 // MPU Region Size 4 MBytes
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rs8MB regionSize = 0x16 // MPU Region Size 8 MBytes
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rs16MB regionSize = 0x17 // MPU Region Size 16 MBytes
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rs32MB regionSize = 0x18 // MPU Region Size 32 MBytes
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rs64MB regionSize = 0x19 // MPU Region Size 64 MBytes
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rs128MB regionSize = 0x1A // MPU Region Size 128 MBytes
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rs256MB regionSize = 0x1B // MPU Region Size 256 MBytes
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rs512MB regionSize = 0x1C // MPU Region Size 512 MBytes
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rs1GB regionSize = 0x1D // MPU Region Size 1 GByte
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rs2GB regionSize = 0x1E // MPU Region Size 2 GBytes
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rs4GB regionSize = 0x1F // MPU Region Size 4 GBytes
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)
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type accessPerms uint32
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const (
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apNone accessPerms = 0 // MPU Access Permission no access
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apPriv accessPerms = 1 // MPU Access Permission privileged access only
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apURO accessPerms = 2 // MPU Access Permission unprivileged access read-only
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apFull accessPerms = 3 // MPU Access Permission full access
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apPRO accessPerms = 5 // MPU Access Permission privileged access read-only
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apRO accessPerms = 6 // MPU Access Permission read-only access
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)
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type extension uint32
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const (
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exNormal extension = 0
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exDevice extension = 2
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)
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func (mpu *MPU_Type) enable(enable bool) {
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if enable {
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mpu.CTRL.Set(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk)
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nxp.SystemControl.SHCSR.SetBits(nxp.SCB_SHCSR_MEMFAULTENA_Msk)
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arm.AsmFull(`
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dsb 0xF
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isb 0xF
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`, nil)
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enableDcache(true)
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enableIcache(true)
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} else {
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enableIcache(false)
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enableDcache(false)
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arm.AsmFull(`
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dmb 0xF
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`, nil)
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nxp.SystemControl.SHCSR.ClearBits(nxp.SCB_SHCSR_MEMFAULTENA_Msk)
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mpu.CTRL.ClearBits(MPU_CTRL_ENABLE_Msk)
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}
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}
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// MPU Region Base Address Register value
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func (mpu *MPU_Type) setRBAR(region uint32, baseAddress uint32) {
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mpu.RBAR.Set((baseAddress & MPU_RBAR_ADDR_Msk) |
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(region & MPU_RBAR_REGION_Msk) | MPU_RBAR_VALID_Msk)
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}
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// MPU Region Attribute and Size Register value
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func (mpu *MPU_Type) setRASR(size regionSize, access accessPerms, ext extension, exec, share, cache, buffer, disable bool) {
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boolBit := func(b bool) uint32 {
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if b {
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return 1
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}
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return 0
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}
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attr := ((uint32(ext) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) |
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((boolBit(share) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) |
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((boolBit(cache) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) |
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((boolBit(buffer) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)
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mpu.RASR.Set(((boolBit(!exec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) |
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((uint32(access) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) |
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(attr & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)) |
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((boolBit(disable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) |
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((uint32(size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) |
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MPU_RASR_ENABLE_Msk)
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}
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func enableIcache(enable bool) {
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if enable != nxp.SystemControl.CCR.HasBits(nxp.SCB_CCR_IC_Msk) {
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if enable {
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arm.AsmFull(`
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dsb 0xF
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isb 0xF
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`, nil)
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nxp.SystemControl.ICIALLU.Set(0)
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arm.AsmFull(`
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dsb 0xF
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isb 0xF
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`, nil)
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nxp.SystemControl.CCR.SetBits(nxp.SCB_CCR_IC_Msk)
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arm.AsmFull(`
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dsb 0xF
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isb 0xF
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`, nil)
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} else {
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arm.AsmFull(`
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dsb 0xF
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isb 0xF
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`, nil)
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nxp.SystemControl.CCR.ClearBits(nxp.SCB_CCR_IC_Msk)
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nxp.SystemControl.ICIALLU.Set(0)
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arm.AsmFull(`
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dsb 0xF
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isb 0xF
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`, nil)
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}
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}
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}
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func enableDcache(enable bool) {
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if enable != nxp.SystemControl.CCR.HasBits(nxp.SCB_CCR_DC_Msk) {
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if enable {
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nxp.SystemControl.CSSELR.Set(0)
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arm.AsmFull(`
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dsb 0xF
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`, nil)
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ccsidr := nxp.SystemControl.CCSIDR.Get()
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sets := (ccsidr & nxp.SCB_CCSIDR_NUMSETS_Msk) >> nxp.SCB_CCSIDR_NUMSETS_Pos
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for sets != 0 {
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ways := (ccsidr & nxp.SCB_CCSIDR_ASSOCIATIVITY_Msk) >> nxp.SCB_CCSIDR_ASSOCIATIVITY_Pos
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for ways != 0 {
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nxp.SystemControl.DCISW.Set(
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((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
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((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk))
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ways--
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}
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sets--
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}
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arm.AsmFull(`
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dsb 0xF
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`, nil)
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nxp.SystemControl.CCR.SetBits(nxp.SCB_CCR_DC_Msk)
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arm.AsmFull(`
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dsb 0xF
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isb 0xF
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`, nil)
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} else {
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var (
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ccsidr volatile.Register32
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sets volatile.Register32
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ways volatile.Register32
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)
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nxp.SystemControl.CSSELR.Set(0)
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arm.AsmFull(`
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dsb 0xF
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`, nil)
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nxp.SystemControl.CCR.ClearBits(nxp.SCB_CCR_DC_Msk)
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arm.AsmFull(`
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dsb 0xF
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`, nil)
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ccsidr.Set(nxp.SystemControl.CCSIDR.Get())
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sets.Set((ccsidr.Get() & nxp.SCB_CCSIDR_NUMSETS_Msk) >> nxp.SCB_CCSIDR_NUMSETS_Pos)
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for sets.Get() != 0 {
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ways.Set((ccsidr.Get() & nxp.SCB_CCSIDR_ASSOCIATIVITY_Msk) >> nxp.SCB_CCSIDR_ASSOCIATIVITY_Pos)
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for ways.Get() != 0 {
|
||||
nxp.SystemControl.DCCISW.Set(
|
||||
((sets.Get() << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways.Get() << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk))
|
||||
ways.Set(ways.Get() - 1)
|
||||
}
|
||||
sets.Set(sets.Get() - 1)
|
||||
}
|
||||
arm.AsmFull(`
|
||||
dsb 0xF
|
||||
isb 0xF
|
||||
`, nil)
|
||||
}
|
||||
}
|
||||
nxp.MPU.Enable(true)
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user