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Code Issues Packages Projects Releases 6 Wiki Activity

mimxrt1062: move device-specific files to "device/nxp" package

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This commit is contained in:
ardnew
2020-10-22 17:13:07 -05:00
committed by Ron Evans
parent 691185f5f4
commit f93b28057a
10 changed files with 1480 additions and 1424 deletions
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src/runtime/runtime_cortexm_hardfault_config.go
-27
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@@ -1,27 +0,0 @@
// +build nxp,!mimxrt1062
package runtime
import "device/nxp"
const (
CFSR_IACCVIOL = nxp.SystemControl_CFSR_IACCVIOL
CFSR_DACCVIOL = nxp.SystemControl_CFSR_DACCVIOL
CFSR_MUNSTKERR = nxp.SystemControl_CFSR_MUNSTKERR
CFSR_MSTKERR = nxp.SystemControl_CFSR_MSTKERR
CFSR_MLSPERR = nxp.SystemControl_CFSR_MLSPERR
CFSR_IBUSERR = nxp.SystemControl_CFSR_IBUSERR
CFSR_PRECISERR = nxp.SystemControl_CFSR_PRECISERR
CFSR_IMPRECISERR = nxp.SystemControl_CFSR_IMPRECISERR
CFSR_UNSTKERR = nxp.SystemControl_CFSR_UNSTKERR
CFSR_STKERR = nxp.SystemControl_CFSR_STKERR
CFSR_LSPERR = nxp.SystemControl_CFSR_LSPERR
CFSR_UNDEFINSTR = nxp.SystemControl_CFSR_UNDEFINSTR
CFSR_INVSTATE = nxp.SystemControl_CFSR_INVSTATE
CFSR_INVPC = nxp.SystemControl_CFSR_INVPC
CFSR_NOCP = nxp.SystemControl_CFSR_NOCP
CFSR_UNALIGNED = nxp.SystemControl_CFSR_UNALIGNED
CFSR_DIVBYZERO = nxp.SystemControl_CFSR_DIVBYZERO
CFSR_MMARVALID = nxp.SystemControl_CFSR_MMARVALID
CFSR_BFARVALID = nxp.SystemControl_CFSR_BFARVALID
)
src/runtime/runtime_cortexm_hardfault_config_mimxrt1062.go
-27
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@@ -1,27 +0,0 @@
// +build nxp,mimxrt1062
package runtime
import "device/nxp"
const (
CFSR_IACCVIOL = nxp.SCB_CFSR_IACCVIOL
CFSR_DACCVIOL = nxp.SCB_CFSR_DACCVIOL
CFSR_MUNSTKERR = nxp.SCB_CFSR_MUNSTKERR
CFSR_MSTKERR = nxp.SCB_CFSR_MSTKERR
CFSR_MLSPERR = nxp.SCB_CFSR_MLSPERR
CFSR_IBUSERR = nxp.SCB_CFSR_IBUSERR
CFSR_PRECISERR = nxp.SCB_CFSR_PRECISERR
CFSR_IMPRECISERR = nxp.SCB_CFSR_IMPRECISERR
CFSR_UNSTKERR = nxp.SCB_CFSR_UNSTKERR
CFSR_STKERR = nxp.SCB_CFSR_STKERR
CFSR_LSPERR = nxp.SCB_CFSR_LSPERR
CFSR_UNDEFINSTR = nxp.SCB_CFSR_UNDEFINSTR
CFSR_INVSTATE = nxp.SCB_CFSR_INVSTATE
CFSR_INVPC = nxp.SCB_CFSR_INVPC
CFSR_NOCP = nxp.SCB_CFSR_NOCP
CFSR_UNALIGNED = nxp.SCB_CFSR_UNALIGNED
CFSR_DIVBYZERO = nxp.SCB_CFSR_DIVBYZERO
CFSR_MMARVALID = nxp.SCB_CFSR_MMARVALID
CFSR_BFARVALID = nxp.SCB_CFSR_BFARVALID
)
src/runtime/runtime_cortexm_hardfault_debug.go
+54 -26
View File
@@ -8,11 +8,15 @@ import (
)
const (
SystemControl_CFSR_KnownFault = CFSR_IACCVIOL | CFSR_DACCVIOL |
CFSR_MUNSTKERR | CFSR_MSTKERR | CFSR_MLSPERR | CFSR_IBUSERR |
CFSR_PRECISERR | CFSR_IMPRECISERR | CFSR_UNSTKERR | CFSR_STKERR |
CFSR_LSPERR | CFSR_UNDEFINSTR | CFSR_INVSTATE | CFSR_INVPC | CFSR_NOCP |
CFSR_UNALIGNED | CFSR_DIVBYZERO
SystemControl_CFSR_KnownFault = nxp.HardFault_CFSR_IACCVIOL |
nxp.HardFault_CFSR_DACCVIOL | nxp.HardFault_CFSR_MUNSTKERR |
nxp.HardFault_CFSR_MSTKERR | nxp.HardFault_CFSR_MLSPERR |
nxp.HardFault_CFSR_IBUSERR | nxp.HardFault_CFSR_PRECISERR |
nxp.HardFault_CFSR_IMPRECISERR | nxp.HardFault_CFSR_UNSTKERR |
nxp.HardFault_CFSR_STKERR | nxp.HardFault_CFSR_LSPERR |
nxp.HardFault_CFSR_UNDEFINSTR | nxp.HardFault_CFSR_INVSTATE |
nxp.HardFault_CFSR_INVPC | nxp.HardFault_CFSR_NOCP |
nxp.HardFault_CFSR_UNALIGNED | nxp.HardFault_CFSR_DIVBYZERO
)
// See runtime_cortexm_hardfault.go
@@ -108,7 +112,9 @@ func handleHardFault(sp *interruptStack) {
// GetFaultStatus reads the System Control Block Configurable Fault Status
// Register and returns it as a FaultStatus.
func GetFaultStatus() FaultStatus { return FaultStatus(nxp.SystemControl.CFSR.Get()) }
func GetFaultStatus() FaultStatus {
return FaultStatus(nxp.SystemControl.CFSR.Get())
}
type FaultStatus uint32
type MemFaultStatus uint32
@@ -120,7 +126,9 @@ func (fs FaultStatus) Bus() BusFaultStatus { return BusFaultStatus(fs) }
func (fs FaultStatus) Usage() UsageFaultStatus { return UsageFaultStatus(fs) }
// Unknown returns true if the cause of the fault is not know
func (fs FaultStatus) Unknown() bool { return fs&SystemControl_CFSR_KnownFault == 0 }
func (fs FaultStatus) Unknown() bool {
return fs&SystemControl_CFSR_KnownFault == 0
}
// InstructionAccessViolation: the processor attempted an instruction fetch from
// a location that does not permit execution
@@ -132,7 +140,7 @@ func (fs FaultStatus) Unknown() bool { return fs&SystemControl_CFSR_KnownFault =
// the faulting instruction. The processor has not written a fault address to
// the MMAR."
func (fs MemFaultStatus) InstructionAccessViolation() bool {
return fs&CFSR_IACCVIOL != 0
return fs&nxp.HardFault_CFSR_IACCVIOL != 0
}
// DataAccessViolation: the processor attempted a load or store at a location
@@ -141,7 +149,9 @@ func (fs MemFaultStatus) InstructionAccessViolation() bool {
// "When this bit is 1, the PC value stacked for the exception return points to
// the faulting instruction. The processor has loaded the MMAR with the address
// of the attempted access."
func (fs MemFaultStatus) DataAccessViolation() bool { return fs&CFSR_DACCVIOL != 0 }
func (fs MemFaultStatus) DataAccessViolation() bool {
return fs&nxp.HardFault_CFSR_DACCVIOL != 0
}
// WhileUnstackingException: unstack for an exception return has caused one or
// more access violations
@@ -151,7 +161,7 @@ func (fs MemFaultStatus) DataAccessViolation() bool { return fs&CFSR_DACCVIOL !=
// the SP from the failing return, and has not performed a new save. The
// processor has not written a fault address to the MMAR."
func (fs MemFaultStatus) WhileUnstackingException() bool {
return fs&CFSR_MUNSTKERR != 0
return fs&nxp.HardFault_CFSR_MUNSTKERR != 0
}
// WileStackingException: stacking for an exception entry has caused one or more
@@ -160,11 +170,15 @@ func (fs MemFaultStatus) WhileUnstackingException() bool {
// "When this bit is 1, the SP is still adjusted but the values in the context
// area on the stack might be incorrect. The processor has not written a fault
// address to the MMAR."
func (fs MemFaultStatus) WileStackingException() bool { return fs&CFSR_MSTKERR != 0 }
func (fs MemFaultStatus) WileStackingException() bool {
return fs&nxp.HardFault_CFSR_MSTKERR != 0
}
// DuringFPLazyStatePres: A MemManage fault occurred during floating-point lazy
// state preservation
func (fs MemFaultStatus) DuringFPLazyStatePres() bool { return fs&CFSR_MLSPERR != 0 }
func (fs MemFaultStatus) DuringFPLazyStatePres() bool {
return fs&nxp.HardFault_CFSR_MLSPERR != 0
}
// InstructionBusError: instruction bus error
//
@@ -174,11 +188,15 @@ func (fs MemFaultStatus) DuringFPLazyStatePres() bool { return fs&CFSR_MLSPERR !
//
// When the processor sets this bit is 1, it does not write a fault address to
// the BFAR."
func (fs BusFaultStatus) InstructionBusError() bool { return fs&CFSR_IBUSERR != 0 }
func (fs BusFaultStatus) InstructionBusError() bool {
return fs&nxp.HardFault_CFSR_IBUSERR != 0
}
// PreciseDataBusError: a data bus error has occurred, and the PC value stacked
// for the exception return points to the instruction that caused the fault
func (fs BusFaultStatus) PreciseDataBusError() bool { return fs&CFSR_PRECISERR != 0 }
func (fs BusFaultStatus) PreciseDataBusError() bool {
return fs&nxp.HardFault_CFSR_PRECISERR != 0
}
// ImpreciseDataBusError: a data bus error has occurred, but the return address
// in the stack frame is not related to the instruction that caused the error
@@ -193,7 +211,7 @@ func (fs BusFaultStatus) PreciseDataBusError() bool { return fs&CFSR_PRECISERR !
// enters the handler for the imprecise BusFault, the handler detects both
// IMPRECISERR set to 1 and one of the precise fault status bits set to 1."
func (fs BusFaultStatus) ImpreciseDataBusError() bool {
return fs&CFSR_IMPRECISERR != 0
return fs&nxp.HardFault_CFSR_IMPRECISERR != 0
}
// WhileUnstackingException: unstack for an exception return has caused one or
@@ -204,7 +222,7 @@ func (fs BusFaultStatus) ImpreciseDataBusError() bool {
// does not adjust the SP from the failing return, does not performed a new
// save, and does not write a fault address to the BFAR."
func (fs BusFaultStatus) WhileUnstackingException() bool {
return fs&CFSR_UNSTKERR != 0
return fs&nxp.HardFault_CFSR_UNSTKERR != 0
}
// WhileStackingException: stacking for an exception entry has caused one or
@@ -213,11 +231,15 @@ func (fs BusFaultStatus) WhileUnstackingException() bool {
// "When the processor sets this bit to 1, the SP is still adjusted but the
// values in the context area on the stack might be incorrect. The processor
// does not write a fault address to the BFAR."
func (fs BusFaultStatus) WhileStackingException() bool { return fs&CFSR_STKERR != 0 }
func (fs BusFaultStatus) WhileStackingException() bool {
return fs&nxp.HardFault_CFSR_STKERR != 0
}
// DuringFPLazyStatePres: A bus fault occurred during floating-point lazy state
// preservation
func (fs BusFaultStatus) DuringFPLazyStatePres() bool { return fs&CFSR_LSPERR != 0 }
func (fs BusFaultStatus) DuringFPLazyStatePres() bool {
return fs&nxp.HardFault_CFSR_LSPERR != 0
}
// UndefinedInstruction: the processor has attempted to execute an undefined
// instruction
@@ -227,7 +249,7 @@ func (fs BusFaultStatus) DuringFPLazyStatePres() bool { return fs&CFSR_LSPERR !=
//
// An undefined instruction is an instruction that the processor cannot decode."
func (fs UsageFaultStatus) UndefinedInstruction() bool {
return fs&CFSR_UNDEFINSTR != 0
return fs&nxp.HardFault_CFSR_UNDEFINSTR != 0
}
// IllegalUseOfEPSR: the processor has attempted to execute an instruction that
@@ -237,19 +259,23 @@ func (fs UsageFaultStatus) UndefinedInstruction() bool {
// points to the instruction that attempted the illegal use of the EPSR.
//
// This bit is not set to 1 if an undefined instruction uses the EPSR."
func (fs UsageFaultStatus) IllegalUseOfEPSR() bool { return fs&CFSR_INVSTATE != 0 }
func (fs UsageFaultStatus) IllegalUseOfEPSR() bool {
return fs&nxp.HardFault_CFSR_INVSTATE != 0
}
// IllegalExceptionReturn: the processor has attempted an illegal load of
// EXC_RETURN to the PC
//
// "When this bit is set to 1, the PC value stacked for the exception return
// points to the instruction that tried to perform the illegal load of the PC."
func (fs UsageFaultStatus) IllegalExceptionReturn() bool { return fs&CFSR_INVPC != 0 }
func (fs UsageFaultStatus) IllegalExceptionReturn() bool {
return fs&nxp.HardFault_CFSR_INVPC != 0
}
// AttemptedToAccessCoprocessor: the processor has attempted to access a
// coprocessor
func (fs UsageFaultStatus) AttemptedToAccessCoprocessor() bool {
return fs&CFSR_NOCP != 0
return fs&nxp.HardFault_CFSR_NOCP != 0
}
// UnalignedMemoryAccess: the processor has made an unaligned memory access
@@ -260,7 +286,7 @@ func (fs UsageFaultStatus) AttemptedToAccessCoprocessor() bool {
// Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of
// the setting of UNALIGN_TRP."
func (fs UsageFaultStatus) UnalignedMemoryAccess() bool {
return fs&CFSR_UNALIGNED != 0
return fs&nxp.HardFault_CFSR_UNALIGNED != 0
}
// DivideByZero: the processor has executed an SDIV or UDIV instruction with a
@@ -271,7 +297,9 @@ func (fs UsageFaultStatus) UnalignedMemoryAccess() bool {
//
// Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to
// 1."
func (fs UsageFaultStatus) DivideByZero() bool { return fs&CFSR_DIVBYZERO != 0 }
func (fs UsageFaultStatus) DivideByZero() bool {
return fs&nxp.HardFault_CFSR_DIVBYZERO != 0
}
// Address returns the MemManage Fault Address Register if the fault status
// indicates the address is valid.
@@ -281,7 +309,7 @@ func (fs UsageFaultStatus) DivideByZero() bool { return fs&CFSR_DIVBYZERO != 0 }
// problems on return to a stacked active MemManage fault handler whose MMAR
// value has been overwritten."
func (fs MemFaultStatus) Address() (uintptr, bool) {
if fs&CFSR_MMARVALID == 0 {
if fs&nxp.HardFault_CFSR_MMARVALID == 0 {
return 0, false
} else {
return uintptr(nxp.SystemControl.MMFAR.Get()), true
@@ -300,7 +328,7 @@ func (fs MemFaultStatus) Address() (uintptr, bool) {
// returning to a stacked active BusFault handler whose BFAR value has been
// overwritten.""
func (fs BusFaultStatus) Address() (uintptr, bool) {
if fs&CFSR_BFARVALID == 0 {
if fs&nxp.HardFault_CFSR_BFARVALID == 0 {
return 0, false
} else {
return uintptr(nxp.SystemControl.BFAR.Get()), true
src/runtime/runtime_mimxrt1062.go
+27 -8
View File
@@ -5,6 +5,7 @@ package runtime
import (
"device/arm"
"device/nxp"
"math/bits"
"unsafe"
)
@@ -46,21 +47,37 @@ func main() {
abort()
}
func getRamSizeConfig(itcmKB, dtcmKB uint32) uint32 {
const minKB, disabled = uint32(4), uint32(0)
if itcmKB < minKB {
itcmKB = disabled
}
if dtcmKB < minKB {
dtcmKB = disabled
}
itcmKB = uint32(bits.Len(uint(itcmKB))) << nxp.IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_Pos
dtcmKB = uint32(bits.Len(uint(dtcmKB))) << nxp.IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_Pos
return (itcmKB & nxp.IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_Msk) |
(dtcmKB & nxp.IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_Msk)
}
func initSystem() {
// configure SRAM capacity
// configure SRAM capacity (512K for both ITCM and DTCM)
ramc := uintptr(unsafe.Pointer(&_flexram_cfg))
nxp.IOMUXC_GPR.GPR17.Set(uint32(ramc))
nxp.IOMUXC_GPR.GPR16.Set(0x00200007)
nxp.IOMUXC_GPR.GPR14.Set(0x00AA0000)
nxp.IOMUXC_GPR.GPR14.Set(getRamSizeConfig(512, 512))
// use bandgap-based bias currents for best performance (Page 1175) [Teensyduino]
nxp.PMU.MISC0_SET.Set(1 << 3)
// from Teensyduino
nxp.PMU.MISC0_SET.Set(nxp.PMU_MISC0_REFTOP_SELFBIASOFF)
// install vector table (TODO: initialize interrupt/exception table?)
vtor := uintptr(unsafe.Pointer(&_svectors))
nxp.SystemControl.VTOR.Set(uint32(vtor))
const wdogUpdateKey = 0xD928C520
// disable watchdog powerdown counter
nxp.WDOG1.WMCR.ClearBits(nxp.WDOG_WMCR_PDE_Msk)
nxp.WDOG2.WMCR.ClearBits(nxp.WDOG_WMCR_PDE_Msk)
@@ -73,10 +90,10 @@ func initSystem() {
nxp.WDOG2.WCR.ClearBits(nxp.WDOG_WCR_WDE_Msk)
}
if nxp.RTWDOG.CS.HasBits(nxp.RTWDOG_CS_CMD32EN_Msk) {
nxp.RTWDOG.CNT.Set(0xD928C520) // 0xD928C520 is the update key
nxp.RTWDOG.CNT.Set(wdogUpdateKey)
} else {
nxp.RTWDOG.CNT.Set(0xC520)
nxp.RTWDOG.CNT.Set(0xD928)
nxp.RTWDOG.CNT.Set((wdogUpdateKey >> 0) & 0xFFFF)
nxp.RTWDOG.CNT.Set((wdogUpdateKey >> 16) & 0xFFFF)
}
nxp.RTWDOG.TOVAL.Set(0xFFFF)
nxp.RTWDOG.CS.Set((nxp.RTWDOG.CS.Get() & ^uint32(nxp.RTWDOG_CS_EN_Msk)) | nxp.RTWDOG_CS_UPDATE_Msk)
@@ -85,7 +102,9 @@ func initSystem() {
func initPeripherals() {
// enable FPU - set CP10, CP11 full access
nxp.SystemControl.CPACR.SetBits((3 << (10 * 2)) | (3 << (11 * 2)))
nxp.SystemControl.CPACR.SetBits(
((nxp.SCB_CPACR_CP10_CP10_3 << nxp.SCB_CPACR_CP10_Pos) & nxp.SCB_CPACR_CP10_Msk) |
((nxp.SCB_CPACR_CP11_CP11_3 << nxp.SCB_CPACR_CP11_Pos) & nxp.SCB_CPACR_CP11_Msk))
enableTimerClocks() // activate GPT/PIT clock gates
initSysTick() // enable SysTick
src/runtime/runtime_mimxrt1062_clock.go
+188 -1030
View File
File diff suppressed because it is too large Load Diff
src/runtime/runtime_mimxrt1062_mpu.go
+18 -306
View File
@@ -3,35 +3,12 @@
package runtime
import (
"device/arm"
"device/nxp"
"runtime/volatile"
"unsafe"
)
type MPU_Type struct {
TYPE volatile.Register32 // 0x000 (R/ ) - MPU Type Register
CTRL volatile.Register32 // 0x004 (R/W) - MPU Control Register
RNR volatile.Register32 // 0x008 (R/W) - MPU Region RNRber Register
RBAR volatile.Register32 // 0x00C (R/W) - MPU Region Base Address Register
RASR volatile.Register32 // 0x010 (R/W) - MPU Region Attribute and Size Register
RBAR_A1 volatile.Register32 // 0x014 (R/W) - MPU Alias 1 Region Base Address Register
RASR_A1 volatile.Register32 // 0x018 (R/W) - MPU Alias 1 Region Attribute and Size Register
RBAR_A2 volatile.Register32 // 0x01C (R/W) - MPU Alias 2 Region Base Address Register
RASR_A2 volatile.Register32 // 0x020 (R/W) - MPU Alias 2 Region Attribute and Size Register
RBAR_A3 volatile.Register32 // 0x024 (R/W) - MPU Alias 3 Region Base Address Register
RASR_A3 volatile.Register32 // 0x028 (R/W) - MPU Alias 3 Region Attribute and Size Register
}
var MPU = (*MPU_Type)(unsafe.Pointer(uintptr(0xe000ed90)))
func initCache() {
MPU.initialize()
}
func (mpu *MPU_Type) initialize() {
mpu.enable(false)
nxp.MPU.Enable(false)
// -------------------------------------------------------- OVERLAY REGIONS --
@@ -40,310 +17,45 @@ func (mpu *MPU_Type) initialize() {
// [0] Default {OVERLAY}:
// 4 GiB, -access, @device, -exec, -share, -cache, -buffer, -subregion
mpu.setRBAR(0, 0x00000000)
mpu.setRASR(rs4GB, apNone, exDevice, false, false, false, false, false)
nxp.MPU.SetRBAR(0, 0x00000000)
nxp.MPU.SetRASR(nxp.RGNSZ_4GB, nxp.PERM_NONE, nxp.EXTN_DEVICE, false, false, false, false, false)
// [1] Peripherals {OVERLAY}:
// 64 MiB, +ACCESS, @device, +EXEC, -share, -cache, -buffer, -subregion
mpu.setRBAR(1, 0x40000000)
mpu.setRASR(rs64MB, apFull, exDevice, true, false, false, false, false)
nxp.MPU.SetRBAR(1, 0x40000000)
nxp.MPU.SetRASR(nxp.RGNSZ_64MB, nxp.PERM_FULL, nxp.EXTN_DEVICE, true, false, false, false, false)
// [2] RAM {OVERLAY}:
// 1 GiB, +ACCESS, @device, +EXEC, -share, -cache, -buffer, -subregion
mpu.setRBAR(2, 0x00000000)
mpu.setRASR(rs1GB, apFull, exDevice, true, false, false, false, false)
nxp.MPU.SetRBAR(2, 0x00000000)
nxp.MPU.SetRASR(nxp.RGNSZ_1GB, nxp.PERM_FULL, nxp.EXTN_DEVICE, true, false, false, false, false)
// ----------------------------------------------------- PERIPHERAL REGIONS --
// [3] ITCM:
// 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, -cache, -buffer, -subregion
mpu.setRBAR(3, 0x00000000)
mpu.setRASR(rs512KB, apFull, exNormal, true, false, false, false, false)
nxp.MPU.SetRBAR(3, 0x00000000)
nxp.MPU.SetRASR(nxp.RGNSZ_512KB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, false, false, false)
// [4] DTCM:
// 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, -cache, -buffer, -subregion
mpu.setRBAR(4, 0x20000000)
mpu.setRASR(rs512KB, apFull, exNormal, true, false, false, false, false)
nxp.MPU.SetRBAR(4, 0x20000000)
nxp.MPU.SetRASR(nxp.RGNSZ_512KB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, false, false, false)
// [5] RAM (AXI):
// 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion
mpu.setRBAR(5, 0x20200000)
mpu.setRASR(rs512KB, apFull, exNormal, true, false, true, true, false)
nxp.MPU.SetRBAR(5, 0x20200000)
nxp.MPU.SetRASR(nxp.RGNSZ_512KB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, true, true, false)
// [6] FlexSPI:
// 512 MiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion
mpu.setRBAR(6, 0x70000000)
mpu.setRASR(rs512MB, apFull, exNormal, true, false, true, true, false)
nxp.MPU.SetRBAR(6, 0x70000000)
nxp.MPU.SetRASR(nxp.RGNSZ_512MB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, true, true, false)
// [7] QSPI flash:
// 2 MiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion
mpu.setRBAR(7, 0x60000000)
mpu.setRASR(rs2MB, apFull, exNormal, true, false, true, true, false)
nxp.MPU.SetRBAR(7, 0x60000000)
nxp.MPU.SetRASR(nxp.RGNSZ_2MB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, true, true, false)
mpu.enable(true)
}
// MPU Type Register Definitions
const (
MPU_TYPE_IREGION_Pos = 16 // MPU TYPE: IREGION Position
MPU_TYPE_IREGION_Msk = 0xFF << MPU_TYPE_IREGION_Pos // MPU TYPE: IREGION Mask
MPU_TYPE_DREGION_Pos = 8 // MPU TYPE: DREGION Position
MPU_TYPE_DREGION_Msk = 0xFF << MPU_TYPE_DREGION_Pos // MPU TYPE: DREGION Mask
MPU_TYPE_SEPARATE_Pos = 0 // MPU TYPE: SEPARATE Position
MPU_TYPE_SEPARATE_Msk = 1 // MPU TYPE: SEPARATE Mask
)
// MPU Control Register Definitions
const (
MPU_CTRL_PRIVDEFENA_Pos = 2 // MPU CTRL: PRIVDEFENA Position
MPU_CTRL_PRIVDEFENA_Msk = 1 << MPU_CTRL_PRIVDEFENA_Pos // MPU CTRL: PRIVDEFENA Mask
MPU_CTRL_HFNMIENA_Pos = 1 // MPU CTRL: HFNMIENA Position
MPU_CTRL_HFNMIENA_Msk = 1 << MPU_CTRL_HFNMIENA_Pos // MPU CTRL: HFNMIENA Mask
MPU_CTRL_ENABLE_Pos = 0 // MPU CTRL: ENABLE Position
MPU_CTRL_ENABLE_Msk = 1 // MPU CTRL: ENABLE Mask
)
// MPU Region Number Register Definitions
const (
MPU_RNR_REGION_Pos = 0 // MPU RNR: REGION Position
MPU_RNR_REGION_Msk = 0xFF // MPU RNR: REGION Mask
)
// MPU Region Base Address Register Definitions
const (
MPU_RBAR_ADDR_Pos = 5 // MPU RBAR: ADDR Position
MPU_RBAR_ADDR_Msk = 0x7FFFFFF << MPU_RBAR_ADDR_Pos // MPU RBAR: ADDR Mask
MPU_RBAR_VALID_Pos = 4 // MPU RBAR: VALID Position
MPU_RBAR_VALID_Msk = 1 << MPU_RBAR_VALID_Pos // MPU RBAR: VALID Mask
MPU_RBAR_REGION_Pos = 0 // MPU RBAR: REGION Position
MPU_RBAR_REGION_Msk = 0xF // MPU RBAR: REGION Mask
)
// MPU Region Attribute and Size Register Definitions
const (
MPU_RASR_ATTRS_Pos = 16 // MPU RASR: MPU Region Attribute field Position
MPU_RASR_ATTRS_Msk = 0xFFFF << MPU_RASR_ATTRS_Pos // MPU RASR: MPU Region Attribute field Mask
MPU_RASR_XN_Pos = 28 // MPU RASR: ATTRS.XN Position
MPU_RASR_XN_Msk = 1 << MPU_RASR_XN_Pos // MPU RASR: ATTRS.XN Mask
MPU_RASR_AP_Pos = 24 // MPU RASR: ATTRS.AP Position
MPU_RASR_AP_Msk = 0x7 << MPU_RASR_AP_Pos // MPU RASR: ATTRS.AP Mask
MPU_RASR_TEX_Pos = 19 // MPU RASR: ATTRS.TEX Position
MPU_RASR_TEX_Msk = 0x7 << MPU_RASR_TEX_Pos // MPU RASR: ATTRS.TEX Mask
MPU_RASR_S_Pos = 18 // MPU RASR: ATTRS.S Position
MPU_RASR_S_Msk = 1 << MPU_RASR_S_Pos // MPU RASR: ATTRS.S Mask
MPU_RASR_C_Pos = 17 // MPU RASR: ATTRS.C Position
MPU_RASR_C_Msk = 1 << MPU_RASR_C_Pos // MPU RASR: ATTRS.C Mask
MPU_RASR_B_Pos = 16 // MPU RASR: ATTRS.B Position
MPU_RASR_B_Msk = 1 << MPU_RASR_B_Pos // MPU RASR: ATTRS.B Mask
MPU_RASR_SRD_Pos = 8 // MPU RASR: Sub-Region Disable Position
MPU_RASR_SRD_Msk = 0xFF << MPU_RASR_SRD_Pos // MPU RASR: Sub-Region Disable Mask
MPU_RASR_SIZE_Pos = 1 // MPU RASR: Region Size Field Position
MPU_RASR_SIZE_Msk = 0x1F << MPU_RASR_SIZE_Pos // MPU RASR: Region Size Field Mask
MPU_RASR_ENABLE_Pos = 0 // MPU RASR: Region enable bit Position
MPU_RASR_ENABLE_Msk = 1 // MPU RASR: Region enable bit Disable Mask
)
const (
SCB_DCISW_WAY_Pos = 30 // SCB DCISW: Way Position
SCB_DCISW_WAY_Msk = 3 << SCB_DCISW_WAY_Pos // SCB DCISW: Way Mask
SCB_DCISW_SET_Pos = 5 // SCB DCISW: Set Position
SCB_DCISW_SET_Msk = 0x1FF << SCB_DCISW_SET_Pos // SCB DCISW: Set Mask
)
const (
SCB_DCCISW_WAY_Pos = 30 // SCB DCCISW: Way Position
SCB_DCCISW_WAY_Msk = 3 << SCB_DCCISW_WAY_Pos // SCB DCCISW: Way Mask
SCB_DCCISW_SET_Pos = 5 // SCB DCCISW: Set Position
SCB_DCCISW_SET_Msk = 0x1FF << SCB_DCCISW_SET_Pos // SCB DCCISW: Set Mask
)
type regionSize uint32
const (
rs32B regionSize = 0x04 // MPU Region Size 32 Bytes
rs64B regionSize = 0x05 // MPU Region Size 64 Bytes
rs128B regionSize = 0x06 // MPU Region Size 128 Bytes
rs256B regionSize = 0x07 // MPU Region Size 256 Bytes
rs512B regionSize = 0x08 // MPU Region Size 512 Bytes
rs1KB regionSize = 0x09 // MPU Region Size 1 KByte
rs2KB regionSize = 0x0A // MPU Region Size 2 KBytes
rs4KB regionSize = 0x0B // MPU Region Size 4 KBytes
rs8KB regionSize = 0x0C // MPU Region Size 8 KBytes
rs16KB regionSize = 0x0D // MPU Region Size 16 KBytes
rs32KB regionSize = 0x0E // MPU Region Size 32 KBytes
rs64KB regionSize = 0x0F // MPU Region Size 64 KBytes
rs128KB regionSize = 0x10 // MPU Region Size 128 KBytes
rs256KB regionSize = 0x11 // MPU Region Size 256 KBytes
rs512KB regionSize = 0x12 // MPU Region Size 512 KBytes
rs1MB regionSize = 0x13 // MPU Region Size 1 MByte
rs2MB regionSize = 0x14 // MPU Region Size 2 MBytes
rs4MB regionSize = 0x15 // MPU Region Size 4 MBytes
rs8MB regionSize = 0x16 // MPU Region Size 8 MBytes
rs16MB regionSize = 0x17 // MPU Region Size 16 MBytes
rs32MB regionSize = 0x18 // MPU Region Size 32 MBytes
rs64MB regionSize = 0x19 // MPU Region Size 64 MBytes
rs128MB regionSize = 0x1A // MPU Region Size 128 MBytes
rs256MB regionSize = 0x1B // MPU Region Size 256 MBytes
rs512MB regionSize = 0x1C // MPU Region Size 512 MBytes
rs1GB regionSize = 0x1D // MPU Region Size 1 GByte
rs2GB regionSize = 0x1E // MPU Region Size 2 GBytes
rs4GB regionSize = 0x1F // MPU Region Size 4 GBytes
)
type accessPerms uint32
const (
apNone accessPerms = 0 // MPU Access Permission no access
apPriv accessPerms = 1 // MPU Access Permission privileged access only
apURO accessPerms = 2 // MPU Access Permission unprivileged access read-only
apFull accessPerms = 3 // MPU Access Permission full access
apPRO accessPerms = 5 // MPU Access Permission privileged access read-only
apRO accessPerms = 6 // MPU Access Permission read-only access
)
type extension uint32
const (
exNormal extension = 0
exDevice extension = 2
)
func (mpu *MPU_Type) enable(enable bool) {
if enable {
mpu.CTRL.Set(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk)
nxp.SystemControl.SHCSR.SetBits(nxp.SCB_SHCSR_MEMFAULTENA_Msk)
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
enableDcache(true)
enableIcache(true)
} else {
enableIcache(false)
enableDcache(false)
arm.AsmFull(`
dmb 0xF
`, nil)
nxp.SystemControl.SHCSR.ClearBits(nxp.SCB_SHCSR_MEMFAULTENA_Msk)
mpu.CTRL.ClearBits(MPU_CTRL_ENABLE_Msk)
}
}
// MPU Region Base Address Register value
func (mpu *MPU_Type) setRBAR(region uint32, baseAddress uint32) {
mpu.RBAR.Set((baseAddress & MPU_RBAR_ADDR_Msk) |
(region & MPU_RBAR_REGION_Msk) | MPU_RBAR_VALID_Msk)
}
// MPU Region Attribute and Size Register value
func (mpu *MPU_Type) setRASR(size regionSize, access accessPerms, ext extension, exec, share, cache, buffer, disable bool) {
boolBit := func(b bool) uint32 {
if b {
return 1
}
return 0
}
attr := ((uint32(ext) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) |
((boolBit(share) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) |
((boolBit(cache) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) |
((boolBit(buffer) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)
mpu.RASR.Set(((boolBit(!exec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) |
((uint32(access) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) |
(attr & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)) |
((boolBit(disable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) |
((uint32(size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) |
MPU_RASR_ENABLE_Msk)
}
func enableIcache(enable bool) {
if enable != nxp.SystemControl.CCR.HasBits(nxp.SCB_CCR_IC_Msk) {
if enable {
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
nxp.SystemControl.ICIALLU.Set(0)
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
nxp.SystemControl.CCR.SetBits(nxp.SCB_CCR_IC_Msk)
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
} else {
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
nxp.SystemControl.CCR.ClearBits(nxp.SCB_CCR_IC_Msk)
nxp.SystemControl.ICIALLU.Set(0)
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
}
}
}
func enableDcache(enable bool) {
if enable != nxp.SystemControl.CCR.HasBits(nxp.SCB_CCR_DC_Msk) {
if enable {
nxp.SystemControl.CSSELR.Set(0)
arm.AsmFull(`
dsb 0xF
`, nil)
ccsidr := nxp.SystemControl.CCSIDR.Get()
sets := (ccsidr & nxp.SCB_CCSIDR_NUMSETS_Msk) >> nxp.SCB_CCSIDR_NUMSETS_Pos
for sets != 0 {
ways := (ccsidr & nxp.SCB_CCSIDR_ASSOCIATIVITY_Msk) >> nxp.SCB_CCSIDR_ASSOCIATIVITY_Pos
for ways != 0 {
nxp.SystemControl.DCISW.Set(
((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk))
ways--
}
sets--
}
arm.AsmFull(`
dsb 0xF
`, nil)
nxp.SystemControl.CCR.SetBits(nxp.SCB_CCR_DC_Msk)
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
} else {
var (
ccsidr volatile.Register32
sets volatile.Register32
ways volatile.Register32
)
nxp.SystemControl.CSSELR.Set(0)
arm.AsmFull(`
dsb 0xF
`, nil)
nxp.SystemControl.CCR.ClearBits(nxp.SCB_CCR_DC_Msk)
arm.AsmFull(`
dsb 0xF
`, nil)
ccsidr.Set(nxp.SystemControl.CCSIDR.Get())
sets.Set((ccsidr.Get() & nxp.SCB_CCSIDR_NUMSETS_Msk) >> nxp.SCB_CCSIDR_NUMSETS_Pos)
for sets.Get() != 0 {
ways.Set((ccsidr.Get() & nxp.SCB_CCSIDR_ASSOCIATIVITY_Msk) >> nxp.SCB_CCSIDR_ASSOCIATIVITY_Pos)
for ways.Get() != 0 {
nxp.SystemControl.DCCISW.Set(
((sets.Get() << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways.Get() << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk))
ways.Set(ways.Get() - 1)
}
sets.Set(sets.Get() - 1)
}
arm.AsmFull(`
dsb 0xF
isb 0xF
`, nil)
}
}
nxp.MPU.Enable(true)
}