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begin USB refactor with package machine/usb2
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ardnew
@@ -0,0 +1,194 @@
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// +build mimxrt1062
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package usb2
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// Implementation of USB device controller interface (dci) for NXP iMXRT1062.
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import (
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"device/arm"
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"device/nxp"
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"runtime/interrupt"
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"runtime/volatile"
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"strconv"
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)
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// dciCount defines the number of USB cores to configure for device mode. It is
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// computed as the sum of all declared device configuration descriptors.
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const dciCount = descCDCACMConfigCount
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// dciInterruptPriority defines the priority for all USB device interrupts.
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const dciInterruptPriority = 3
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// deviceController implements USB device controller interface (dci).
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type deviceController struct {
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core *core // Parent USB core this instance is attached to
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port int // USB port index
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id int // deviceControllerInstance index
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bus *nxp.USB_Type
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phy *nxp.USBPHY_Type
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irq interrupt.Interrupt
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cri volatile.Register8 // set to 1 if in critical section, else 0
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ivm uintptr // interrupt state when entering critical section
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}
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// deviceControllerInstance provides statically-allocated instances of each USB
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// device controller configured on this platform.
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var deviceControllerInstance [dciCount]deviceController
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// initDCI initializes and assigns a free device controller instance to the
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// given USB port. Returns the initialized device controller or nil if no free
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// device controller instances remain.
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func initDCI(port int) (dci, status) {
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if 0 == dciCount {
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return nil, statusInvalidArgument // must have defined device descriptors
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}
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// Return the first instance whose assigned core is currently nil.
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for i := range deviceControllerInstance {
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if nil == deviceControllerInstance[i].core {
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// Initialize device controller.
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deviceControllerInstance[i].core = &coreInstance[port]
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deviceControllerInstance[i].port = port
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deviceControllerInstance[i].id = i
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switch port {
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case 0:
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deviceControllerInstance[i].bus = nxp.USB1
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deviceControllerInstance[i].phy = nxp.USBPHY1
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deviceControllerInstance[i].irq =
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interrupt.New(nxp.IRQ_USB_OTG1,
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func(interrupt.Interrupt) {
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coreInstance[0].dc.interrupt()
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})
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case 1:
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deviceControllerInstance[i].bus = nxp.USB2
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deviceControllerInstance[i].phy = nxp.USBPHY2
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deviceControllerInstance[i].irq =
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interrupt.New(nxp.IRQ_USB_OTG2,
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func(interrupt.Interrupt) {
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//coreInstance[1].dc.interrupt()
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})
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}
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return &deviceControllerInstance[i], statusOK
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}
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}
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return nil, statusBusy // No free device controller instances available.
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}
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func (dc *deviceController) init() status {
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dc.bus.BURSTSIZE.Set(0x0404)
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// if dc.phy.PWD.HasBits((nxp.USBPHY_PWD_RXPWDRX | nxp.USBPHY_PWD_RXPWDDIFF |
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// nxp.USBPHY_PWD_RXPWD1PT1 | nxp.USBPHY_PWD_RXPWDENV |
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// nxp.USBPHY_PWD_TXPWDV2I | nxp.USBPHY_PWD_TXPWDIBIAS |
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// nxp.USBPHY_PWD_TXPWDFS)) ||
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// dc.bus.USBMODE.HasBits(nxp.USB_USBMODE_CM_Msk) {
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// // reset controller if it was already enabled
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// dc.phy.CTRL_SET.Set(nxp.USBPHY_CTRL_SFTRST)
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// dc.bus.USBCMD.SetBits(nxp.USB_USBCMD_RST)
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// for dc.bus.USBCMD.HasBits(nxp.USB_USBCMD_RST) {
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// }
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// // clear interrupts
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// m := arm.DisableInterrupts()
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// switch dc.port {
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// case 0:
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// arm.EnableInterrupts(m & ^uintptr(nxp.IRQ_USB_OTG1))
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// case 1:
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// arm.EnableInterrupts(m & ^uintptr(nxp.IRQ_USB_OTG2))
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// }
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// dc.phy.CTRL_CLR.Set(nxp.USBPHY_CTRL_SFTRST)
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// }
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// reset the controller
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dc.phy.CTRL_SET.Set(nxp.USBPHY_CTRL_SFTRST)
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dc.bus.USBCMD.SetBits(nxp.USB_USBCMD_RST)
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for dc.bus.USBCMD.HasBits(nxp.USB_USBCMD_RST) {
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}
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// clear interrupts
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m := arm.DisableInterrupts()
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switch dc.port {
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case 0:
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arm.EnableInterrupts(m & ^uintptr(nxp.IRQ_USB_OTG1))
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case 1:
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arm.EnableInterrupts(m & ^uintptr(nxp.IRQ_USB_OTG2))
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}
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dc.phy.CTRL_CLR.Set(nxp.USBPHY_CTRL_CLKGATE | nxp.USBPHY_CTRL_SFTRST)
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dc.phy.PWD.Set(0)
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// clear the controller mode field and set to device mode:
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// controller mode (CM) 0x0=idle, 0x2=device-only, 0x3=host-only
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dc.bus.USBMODE.ReplaceBits(nxp.USB_USBMODE_CM_CM_2,
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nxp.USB_USBMODE_CM_Msk>>nxp.USB_USBMODE_CM_Pos, nxp.USB_USBMODE_CM_Pos)
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dc.bus.USBCMD.ClearBits(nxp.USB_USBCMD_ITC_Msk) // no interrupt threshold
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dc.bus.USBMODE.SetBits(nxp.USB_USBMODE_SLOM_Msk) // disable setup lockout
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dc.bus.USBMODE.ClearBits(nxp.USB_USBMODE_ES_Msk) // use little-endianness
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// configure ENDPOINTLISTADDR
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// enable interrupts
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dc.bus.USBINTR.Set(
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nxp.USB_USBINTR_UE_Msk | // bus enable
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nxp.USB_USBINTR_UEE_Msk | // bus error
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nxp.USB_USBINTR_PCE_Msk | // port change detect
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nxp.USB_USBINTR_URE_Msk | // bus reset
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nxp.USB_USBINTR_SLE) // sleep enable
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// ensure D+ pulled down long enough for host to detect previous disconnect
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dc.udelay(5000)
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return statusOK
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}
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func (dc *deviceController) enable(enable bool) status {
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dc.irq.SetPriority(dciInterruptPriority)
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dc.irq.Enable()
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dc.bus.USBCMD.SetBits(nxp.USB_USBCMD_RS)
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return statusOK
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}
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func (dc *deviceController) critical(enter bool) status {
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if enter {
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// check if critical section already locked
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if dc.cri.Get() != 0 {
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return statusRetry
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}
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// lock critical section
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dc.cri.Set(1)
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// disable interrupts, storing state in receiver
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dc.ivm = arm.DisableInterrupts()
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} else {
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// ensure critical section is locked
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if dc.cri.Get() != 0 {
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// re-enable interrupts, using state stored in receiver
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arm.EnableInterrupts(dc.ivm)
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// unlock critical section
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dc.cri.Set(0)
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}
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}
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return statusOK
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}
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func (dc *deviceController) interrupt() {
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// read and clear the interrupts that fired
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status := dc.bus.USBSTS.Get() & dc.bus.USBINTR.Get()
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dc.bus.USBSTS.Set(status)
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println(strconv.FormatUint(uint64(status), 16))
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}
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// udelay waits for the given number of microseconds before returning.
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// We cannot use the sleep timer from this context (import cycle), but we need
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// an approximate method to spin CPU cycles for short periods of time.
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//go:inline
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func (dc *deviceController) udelay(microsec uint32) {
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n := cycles(microsec, descCPUFrequencyHz)
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for i := uint32(0); i < n; i++ {
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arm.Asm(`nop`)
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}
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}
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