mirror of
https://github.com/tinygo-org/tinygo.git
synced 2026-08-10 05:53:39 +00:00
begin USB refactor with package machine/usb2
This commit is contained in:
ardnew
@@ -7,6 +7,7 @@
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package nxp
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import (
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"device/arm"
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"runtime/volatile"
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"unsafe"
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)
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@@ -377,30 +378,6 @@ func (clk Clock) setCcm(value uint32) {
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}
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}
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func setSysPfd(value ...uint32) {
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for i, val := range value {
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pfd528 := CCM_ANALOG.PFD_528.Get() &
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^((CCM_ANALOG_PFD_528_PFD0_CLKGATE_Msk | CCM_ANALOG_PFD_528_PFD0_FRAC_Msk) << (8 * uint32(i)))
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frac := (val << CCM_ANALOG_PFD_528_PFD0_FRAC_Pos) & CCM_ANALOG_PFD_528_PFD0_FRAC_Msk
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// disable the clock output first
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CCM_ANALOG.PFD_528.Set(pfd528 | (CCM_ANALOG_PFD_528_PFD0_CLKGATE_Msk << (8 * uint32(i))))
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// set the new value and enable output
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CCM_ANALOG.PFD_528.Set(pfd528 | (frac << (8 * uint32(i))))
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}
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}
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func setUsb1Pfd(value ...uint32) {
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for i, val := range value {
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pfd480 := CCM_ANALOG.PFD_480.Get() &
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^((CCM_ANALOG_PFD_480_PFD0_CLKGATE_Msk | CCM_ANALOG_PFD_480_PFD0_FRAC_Msk) << (8 * uint32(i)))
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frac := (val << CCM_ANALOG_PFD_480_PFD0_FRAC_Pos) & CCM_ANALOG_PFD_480_PFD0_FRAC_Msk
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// disable the clock output first
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CCM_ANALOG.PFD_480.Set(pfd480 | (CCM_ANALOG_PFD_480_PFD0_CLKGATE_Msk << (8 * uint32(i))))
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// set the new value and enable output
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CCM_ANALOG.PFD_480.Set(pfd480 | (frac << (8 * uint32(i))))
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}
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}
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// PLL configuration for ARM
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type ClockConfigArmPll struct {
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LoopDivider uint32 // PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*LoopDivider/2.
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@@ -471,59 +448,178 @@ func (cfg ClockConfigSysPll) Configure(pfd ...uint32) {
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setSysPfd(pfd...)
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}
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// PLL configuration for USB
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type ClockConfigUsbPll struct {
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Instance uint8 // USB PLL number (1 or 2)
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LoopDivider uint8 // PLL loop divider: 0 - Fout=Fref*20, 1 - Fout=Fref*22
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Src uint8 // Pll clock source, reference _clock_pll_clk_src
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func setSysPfd(value ...uint32) {
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for i, val := range value {
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pfd528 := CCM_ANALOG.PFD_528.Get() &
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^((CCM_ANALOG_PFD_528_PFD0_CLKGATE_Msk | CCM_ANALOG_PFD_528_PFD0_FRAC_Msk) << (8 * uint32(i)))
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frac := (val << CCM_ANALOG_PFD_528_PFD0_FRAC_Pos) & CCM_ANALOG_PFD_528_PFD0_FRAC_Msk
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// disable the clock output first
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CCM_ANALOG.PFD_528.Set(pfd528 | (CCM_ANALOG_PFD_528_PFD0_CLKGATE_Msk << (8 * uint32(i))))
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// set the new value and enable output
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CCM_ANALOG.PFD_528.Set(pfd528 | (frac << (8 * uint32(i))))
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}
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}
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func (cfg ClockConfigUsbPll) Configure(pfd ...uint32) {
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// PHY configuration for USB HS
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type ClockConfigUsbPhy struct {
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Instance uint8 // USB PHY number (1 or 2)
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XtalFreq uint32 // External reference clock frequency (Hz)
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DCal uint32 // Decode to trim nominal 17.78mA current source
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TxCal45DP uint32 // Decode to trim nominal 45-Ohm series Rp on USB D+
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TxCal45DM uint32 // Decode to trim nominal 45-Ohm series Rp on USB D-
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PllConfig ClockConfigUsbPll
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}
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// Configure initializes the USB HS (480 Mbit/s) PHY and PLL clocks, including
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// the USB +3V regulator (PMU), for use as either USB host or device.
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func (cfg ClockConfigUsbPhy) Configure() {
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var (
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usb *USB_Type
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phy *USBPHY_Type
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chrgDetectReg *volatile.Register32
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chrgDetectMsk uint32
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)
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// Select appropriate peripherals based on receiver Instance
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switch cfg.Instance {
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case 1:
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// bypass PLL first
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src := (uint32(cfg.Src) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_Pos) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_Msk
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CCM_ANALOG.PLL_USB1.Set(
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(CCM_ANALOG.PLL_USB1.Get() & ^uint32(CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_Msk)) |
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CCM_ANALOG_PLL_USB1_BYPASS_Msk | src)
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sel := uint32((cfg.LoopDivider << CCM_ANALOG_PLL_USB1_DIV_SELECT_Pos) & CCM_ANALOG_PLL_USB1_DIV_SELECT_Msk)
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CCM_ANALOG.PLL_USB1_SET.Set(
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(CCM_ANALOG.PLL_USB1.Get() & ^uint32(CCM_ANALOG_PLL_USB1_DIV_SELECT_Msk)) |
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CCM_ANALOG_PLL_USB1_ENABLE_Msk | CCM_ANALOG_PLL_USB1_POWER_Msk |
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CCM_ANALOG_PLL_USB1_EN_USB_CLKS_Msk | sel)
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for !CCM_ANALOG.PLL_USB1.HasBits(CCM_ANALOG_PLL_USB1_LOCK_Msk) {
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}
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// disable bypass
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CCM_ANALOG.PLL_USB1_CLR.Set(CCM_ANALOG_PLL_USB1_BYPASS_Msk)
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// update PFDs after update
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setUsb1Pfd(pfd...)
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usb = USB1 // Select USB1 HS PHY/PLL
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phy = USBPHY1 //
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chrgDetectReg = &USB_ANALOG.USB1_CHRG_DETECT_SET
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chrgDetectMsk = USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CHRG_B |
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USB_ANALOG_USB1_CHRG_DETECT_SET_EN_B
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case 2:
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// bypass PLL first
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src := (uint32(cfg.Src) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_Pos) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_Msk
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CCM_ANALOG.PLL_USB2.Set(
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(CCM_ANALOG.PLL_USB2.Get() & ^uint32(CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_Msk)) |
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CCM_ANALOG_PLL_USB2_BYPASS_Msk | src)
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usb = USB2 // Select USB2 HS PHY/PLL
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phy = USBPHY2 //
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chrgDetectReg = &USB_ANALOG.USB2_CHRG_DETECT_SET
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chrgDetectMsk = USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CHRG_B |
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USB_ANALOG_USB2_CHRG_DETECT_SET_EN_B
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default:
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panic("nxp: invalid USB PHY")
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}
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sel := uint32((cfg.LoopDivider << CCM_ANALOG_PLL_USB2_DIV_SELECT_Pos) & CCM_ANALOG_PLL_USB2_DIV_SELECT_Msk)
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CCM_ANALOG.PLL_USB2.Set(
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(CCM_ANALOG.PLL_USB2.Get() & ^uint32(CCM_ANALOG_PLL_USB2_DIV_SELECT_Msk)) |
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CCM_ANALOG_PLL_USB2_ENABLE_Msk | CCM_ANALOG_PLL_USB2_POWER_Msk |
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CCM_ANALOG_PLL_USB2_EN_USB_CLKS_Msk | sel)
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// Configure and enable USB PLL clocks
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cfg.PllConfig.Configure()
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for !CCM_ANALOG.PLL_USB2.HasBits(CCM_ANALOG_PLL_USB2_LOCK_Msk) {
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// Release PHY from reset
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phy.CTRL.ClearBits(USBPHY_CTRL_SFTRST)
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phy.CTRL.ClearBits(USBPHY_CTRL_CLKGATE)
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// Enable power to USB PHY
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phy.PWD.Set(0)
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phy.CTRL.SetBits(USBPHY_CTRL_ENAUTOCLR_PHY_PWD | USBPHY_CTRL_ENAUTOCLR_CLKGATE |
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// enable support for low-speed device connection, direct and indirect (hub)
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USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3)
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// Enable USB HS clocks gate
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ClockIpUsbOh3.Enable(true)
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// Reset USB peripheral
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usb.USBCMD.SetBits(USB_USBCMD_RST)
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// Add a delay after RST to ensure there is a USB D+ pullup sequence
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nopDelay(400000)
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// Enable USB LDO
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PMU.REG_3P0.Set((PMU.REG_3P0.Get() & ^uint32(PMU_REG_3P0_OUTPUT_TRG_Msk)) |
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(0x17 << PMU_REG_3P0_OUTPUT_TRG_Pos) | PMU_REG_3P0_ENABLE_LINREG)
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// check whether we are connected to USB charger
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chrgDetectReg.Set(chrgDetectMsk)
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// Decode to trim nominal 17.78mA source for HS TX on USB D+/D-
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phy.TX.Set((phy.TX.Get() &
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^uint32(USBPHY_TX_D_CAL_Msk|USBPHY_TX_TXCAL45DN_Msk|USBPHY_TX_TXCAL45DP_Msk)) |
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((cfg.DCal << USBPHY_TX_D_CAL_Pos) & USBPHY_TX_D_CAL_Msk) |
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((cfg.TxCal45DM << USBPHY_TX_TXCAL45DN_Pos) & USBPHY_TX_TXCAL45DN_Msk) |
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((cfg.TxCal45DP << USBPHY_TX_TXCAL45DP_Pos) & USBPHY_TX_TXCAL45DP_Msk))
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}
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// PLL configuration for USB
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type ClockConfigUsbPll struct {
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Instance uint8 // USB PLL number (1 or 2)
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LoopDivider uint8 // PLL loop divider (0 [Fout=Fref*20] or 1 [Fout=Fref*22])
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Src uint8 // PLL bypass clock source (0 [OSC24M] or 1 [CLK1_P & CLK1_N])
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Pfd []uint32 // Phase fractional divisors (len=4, or nil for boot default)
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}
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func (cfg ClockConfigUsbPll) Configure() {
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// select USB peripheral registers based on receiver's Instance
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switch cfg.Instance {
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case 1: // USB1 PLL
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if CCM_ANALOG.PLL_USB1.HasBits(CCM_ANALOG_PLL_USB1_ENABLE) {
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// PLL already configured, enable USB clocks
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CCM_ANALOG.PLL_USB1.SetBits(CCM_ANALOG_PLL_USB1_EN_USB_CLKS)
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} else {
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// bypass PLL first
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src := (uint32(cfg.Src) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_Pos) &
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CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_Msk
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CCM_ANALOG.PLL_USB1.Set(
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(CCM_ANALOG.PLL_USB1.Get() & ^uint32(CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_Msk)) |
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CCM_ANALOG_PLL_USB1_BYPASS | src)
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// reconfigure PLL
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sel := (uint32(cfg.LoopDivider) << CCM_ANALOG_PLL_USB1_DIV_SELECT_Pos) &
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CCM_ANALOG_PLL_USB1_DIV_SELECT_Msk
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CCM_ANALOG.PLL_USB1.Set(
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(CCM_ANALOG.PLL_USB1.Get() & ^uint32(CCM_ANALOG_PLL_USB1_DIV_SELECT_Msk)) |
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CCM_ANALOG_PLL_USB1_ENABLE | CCM_ANALOG_PLL_USB1_POWER |
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CCM_ANALOG_PLL_USB1_EN_USB_CLKS | sel)
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for !CCM_ANALOG.PLL_USB1.HasBits(CCM_ANALOG_PLL_USB1_LOCK) {
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}
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// disable bypass
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CCM_ANALOG.PLL_USB1.ClearBits(CCM_ANALOG_PLL_USB1_BYPASS)
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// update PFDs (if provided)
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if nil != cfg.Pfd {
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setUsb1Pfd(cfg.Pfd...)
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}
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}
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case 2: // USB2 PLL
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if CCM_ANALOG.PLL_USB2.HasBits(CCM_ANALOG_PLL_USB2_ENABLE) {
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// PLL already configured, enable USB clocks
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CCM_ANALOG.PLL_USB2.SetBits(CCM_ANALOG_PLL_USB2_EN_USB_CLKS)
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} else {
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// bypass PLL first
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src := (uint32(cfg.Src) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_Pos) &
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CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_Msk
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CCM_ANALOG.PLL_USB2.Set(
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(CCM_ANALOG.PLL_USB2.Get() & ^uint32(CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_Msk)) |
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CCM_ANALOG_PLL_USB2_BYPASS | src)
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// reconfigure PLL
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sel := (uint32(cfg.LoopDivider) << CCM_ANALOG_PLL_USB2_DIV_SELECT_Pos) &
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CCM_ANALOG_PLL_USB2_DIV_SELECT_Msk
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CCM_ANALOG.PLL_USB2.Set(
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(CCM_ANALOG.PLL_USB2.Get() & ^uint32(CCM_ANALOG_PLL_USB2_DIV_SELECT_Msk)) |
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CCM_ANALOG_PLL_USB2_ENABLE | CCM_ANALOG_PLL_USB2_POWER |
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CCM_ANALOG_PLL_USB2_EN_USB_CLKS | sel)
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for !CCM_ANALOG.PLL_USB2.HasBits(CCM_ANALOG_PLL_USB2_LOCK) {
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}
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// disable bypass
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CCM_ANALOG.PLL_USB2.ClearBits(CCM_ANALOG_PLL_USB2_BYPASS)
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}
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// disable bypass
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CCM_ANALOG.PLL_USB2.ClearBits(CCM_ANALOG_PLL_USB2_BYPASS_Msk)
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default:
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panic("nxp: invalid USB PLL")
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}
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}
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func setUsb1Pfd(value ...uint32) {
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for i, val := range value {
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pfd480 := CCM_ANALOG.PFD_480.Get() &
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^((CCM_ANALOG_PFD_480_PFD0_CLKGATE_Msk | CCM_ANALOG_PFD_480_PFD0_FRAC_Msk) << (8 * uint32(i)))
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frac := (val << CCM_ANALOG_PFD_480_PFD0_FRAC_Pos) & CCM_ANALOG_PFD_480_PFD0_FRAC_Msk
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// disable the clock output first
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CCM_ANALOG.PFD_480.Set(pfd480 | (CCM_ANALOG_PFD_480_PFD0_CLKGATE_Msk << (8 * uint32(i))))
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// set the new value and enable output
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CCM_ANALOG.PFD_480.Set(pfd480 | (frac << (8 * uint32(i))))
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}
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}
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// We cannot use the sleep timer from this context (import cycle), but we need
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// an approximate method to spin CPU cycles for short periods of time.
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// go:inline
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func nopDelay(cycles uint32) {
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for i := uint32(0); i < cycles; i++ {
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arm.Asm(`nop`)
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}
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}
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@@ -216,6 +216,12 @@ func enableIcache(enable bool) {
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}
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}
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var (
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dcacheCcsidr volatile.Register32
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dcacheSets volatile.Register32
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dcacheWays volatile.Register32
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)
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func enableDcache(enable bool) {
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if enable != SystemControl.CCR.HasBits(SCB_CCR_DC_Msk) {
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if enable {
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@@ -244,11 +250,6 @@ func enableDcache(enable bool) {
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isb 0xF
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`, nil)
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} else {
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var (
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ccsidr volatile.Register32
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sets volatile.Register32
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ways volatile.Register32
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)
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SystemControl.CSSELR.Set(0)
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arm.AsmFull(`
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dsb 0xF
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@@ -257,17 +258,17 @@ func enableDcache(enable bool) {
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arm.AsmFull(`
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dsb 0xF
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`, nil)
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ccsidr.Set(SystemControl.CCSIDR.Get())
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sets.Set((ccsidr.Get() & SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos)
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for sets.Get() != 0 {
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ways.Set((ccsidr.Get() & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
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for ways.Get() != 0 {
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dcacheCcsidr.Set(SystemControl.CCSIDR.Get())
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dcacheSets.Set((dcacheCcsidr.Get() & SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos)
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for dcacheSets.Get() != 0 {
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dcacheWays.Set((dcacheCcsidr.Get() & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
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for dcacheWays.Get() != 0 {
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SystemControl.DCCISW.Set(
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((sets.Get() << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
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((ways.Get() << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk))
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ways.Set(ways.Get() - 1)
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((dcacheSets.Get() << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
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((dcacheWays.Get() << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk))
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dcacheWays.Set(dcacheWays.Get() - 1)
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}
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sets.Set(sets.Get() - 1)
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dcacheSets.Set(dcacheSets.Get() - 1)
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}
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arm.AsmFull(`
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dsb 0xF
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