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https://github.com/tinygo-org/tinygo.git
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Add stm32g0b1 support (#5150)
* Add STM32G0B1 target support Introduce support for STM32G0B1 microcontrollers, including target-specific JSON files, linker scripts, and runtime initialization. This update adds hardware support for GPIO, UART, SPI, I2C, timers, and additional board-specific configurations like Nucleo-G0B1RE. * Update STM32G0 clock initialization to 64MHz and adjust related configurations Reconfigure STM32G0 to use a 64MHz system clock via PLL with HSI16 as the source. Update flash latency, prescaler settings, and I2C timing values to reflect the new frequency. * Cleanup * Cleanup * Add STM32G0-specific UART implementation Introduce a new UART implementation for the STM32G0 series with chip-specific setup and configuration methods. Update the generic STM32 UART code to exclude STM32G0. * Refactor STM32G0 runtime and machine code to utilize chip-specific register access functions Simplify and standardize register operations with dedicated setter methods in the STM32G0 runtime and machine code and cleanup redundant syntax. * Remove redundant commented-out APBENR1 register operations in STM32G0 machine code * Introduce FDCAN support for STM32G0B1 series Add FDCAN peripheral implementation targeting STM32G0B1, including support for standard, extended identifiers, and bit rate configuration. Update board files to include FDCAN pins, instances, and clock configuration for Nucleo-G0B1RE and Amken Trio boards.
This commit is contained in:
Amken USA
GitHub
@@ -0,0 +1,567 @@
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//go:build stm32g0
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package machine
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// Peripheral abstraction layer for the stm32g0
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import (
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"device/stm32"
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"runtime/interrupt"
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"runtime/volatile"
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"unsafe"
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)
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const (
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// CPU frequency for STM32G0 (64MHz via PLL: HSI16 / 1 * 8 / 2)
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cpuFreq = 64000000
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)
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func CPUFrequency() uint32 {
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return cpuFreq
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}
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var deviceIDAddr = []uintptr{0x1FFF7590, 0x1FFF7594, 0x1FFF7598}
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// Internal use: configured speed of the APB1 and APB2 timers, this should be kept
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// in sync with any changes to runtime package which configures the oscillators
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// and clock frequencies
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const APB1_TIM_FREQ = 64e6 // 64MHz (PLL: HSI16 / 1 * 8 / 2)
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const APB2_TIM_FREQ = 64e6 // 64MHz (PLL: HSI16 / 1 * 8 / 2)
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const (
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PA0 = portA + 0
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PA1 = portA + 1
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PA2 = portA + 2
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PA3 = portA + 3
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PA4 = portA + 4
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PA5 = portA + 5
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PA6 = portA + 6
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PA7 = portA + 7
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PA8 = portA + 8
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PA9 = portA + 9
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PA10 = portA + 10
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PA11 = portA + 11
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PA12 = portA + 12
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PA13 = portA + 13
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PA14 = portA + 14
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PA15 = portA + 15
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PB0 = portB + 0
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PB1 = portB + 1
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PB2 = portB + 2
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PB3 = portB + 3
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PB4 = portB + 4
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PB5 = portB + 5
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PB6 = portB + 6
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PB7 = portB + 7
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PB8 = portB + 8
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PB9 = portB + 9
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PB10 = portB + 10
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PB11 = portB + 11
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PB12 = portB + 12
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PB13 = portB + 13
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PB14 = portB + 14
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PB15 = portB + 15
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PC0 = portC + 0
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PC1 = portC + 1
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PC2 = portC + 2
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PC3 = portC + 3
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PC4 = portC + 4
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PC5 = portC + 5
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PC6 = portC + 6
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PC7 = portC + 7
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PC8 = portC + 8
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PC9 = portC + 9
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PC10 = portC + 10
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PC11 = portC + 11
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PC12 = portC + 12
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PC13 = portC + 13
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PC14 = portC + 14
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PC15 = portC + 15
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PD0 = portD + 0
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PD1 = portD + 1
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PD2 = portD + 2
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PD3 = portD + 3
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PD4 = portD + 4
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PD5 = portD + 5
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PD6 = portD + 6
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PD7 = portD + 7
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PD8 = portD + 8
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PD9 = portD + 9
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PD10 = portD + 10
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PD11 = portD + 11
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PD12 = portD + 12
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PD13 = portD + 13
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PD14 = portD + 14
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PD15 = portD + 15
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PE0 = portE + 0
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PE1 = portE + 1
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PE2 = portE + 2
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PE3 = portE + 3
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PE4 = portE + 4
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PE5 = portE + 5
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PE6 = portE + 6
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PE7 = portE + 7
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PE8 = portE + 8
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PE9 = portE + 9
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PE10 = portE + 10
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PE11 = portE + 11
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PE12 = portE + 12
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PE13 = portE + 13
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PE14 = portE + 14
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PE15 = portE + 15
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PF0 = portF + 0
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PF1 = portF + 1
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PF2 = portF + 2
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PF3 = portF + 3
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PF4 = portF + 4
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PF5 = portF + 5
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PF6 = portF + 6
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PF7 = portF + 7
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PF8 = portF + 8
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PF9 = portF + 9
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PF10 = portF + 10
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PF11 = portF + 11
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PF12 = portF + 12
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PF13 = portF + 13
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PF14 = portF + 14
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PF15 = portF + 15
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)
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func (p Pin) getPort() *stm32.GPIO_Type {
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switch p / 16 {
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case 0:
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return stm32.GPIOA
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case 1:
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return stm32.GPIOB
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case 2:
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return stm32.GPIOC
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case 3:
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return stm32.GPIOD
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case 4:
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return stm32.GPIOE
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case 5:
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return stm32.GPIOF
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default:
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panic("machine: unknown port")
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}
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}
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// enableClock enables the clock for this desired GPIO port.
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func (p Pin) enableClock() {
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switch p / 16 {
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case 0:
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stm32.RCC.SetIOPENR_GPIOAEN(1)
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case 1:
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stm32.RCC.SetIOPENR_GPIOBEN(1)
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case 2:
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stm32.RCC.SetIOPENR_GPIOCEN(1)
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case 3:
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stm32.RCC.SetIOPENR_GPIODEN(1)
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case 4:
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stm32.RCC.SetIOPENR_GPIOEEN(1)
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case 5:
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stm32.RCC.SetIOPENR_GPIOFEN(1)
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default:
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panic("machine: unknown port")
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}
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}
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func (p Pin) registerInterrupt() interrupt.Interrupt {
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pin := uint8(p) % 16
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switch pin {
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case 0:
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return interrupt.New(stm32.IRQ_EXTI0_1, func(interrupt.Interrupt) { handlePinInterrupt(0) })
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case 1:
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return interrupt.New(stm32.IRQ_EXTI0_1, func(interrupt.Interrupt) { handlePinInterrupt(1) })
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case 2:
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return interrupt.New(stm32.IRQ_EXTI2_3, func(interrupt.Interrupt) { handlePinInterrupt(2) })
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case 3:
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return interrupt.New(stm32.IRQ_EXTI2_3, func(interrupt.Interrupt) { handlePinInterrupt(3) })
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case 4:
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return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(4) })
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case 5:
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return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(5) })
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case 6:
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return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(6) })
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case 7:
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return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(7) })
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case 8:
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return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(8) })
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case 9:
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return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(9) })
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case 10:
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return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(10) })
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case 11:
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return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(11) })
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case 12:
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return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(12) })
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case 13:
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return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(13) })
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case 14:
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return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(14) })
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case 15:
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return interrupt.New(stm32.IRQ_EXTI4_15, func(interrupt.Interrupt) { handlePinInterrupt(15) })
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}
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return interrupt.Interrupt{}
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}
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//---------- UART related types and code
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// Configure the UART.
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func (uart *UART) configurePins(config UARTConfig) {
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// enable the alternate functions on the TX and RX pins
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config.TX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTTX}, uart.TxAltFuncSelector)
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config.RX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTRX}, uart.RxAltFuncSelector)
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}
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// UART baudrate calc based on the bus and clockspeed
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func (uart *UART) getBaudRateDivisor(baudRate uint32) uint32 {
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return CPUFrequency() / baudRate
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}
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// Register names vary by ST processor, these are for STM G0 family
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func (uart *UART) setRegisters() {
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uart.rxReg = &uart.Bus.RDR
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uart.txReg = &uart.Bus.TDR
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uart.statusReg = &uart.Bus.ISR_FIFO_ENABLED
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uart.txEmptyFlag = stm32.USART_ISR_TXE
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}
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//---------- SPI related types and code
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// SPI on the STM32G0 using MODER / alternate function pins
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type SPI struct {
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Bus *stm32.SPI_Type
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AltFuncSelector uint8
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}
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func (spi *SPI) config8Bits() {
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// Set rx threshold to 8-bits, so RXNE flag is set for 1 byte
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spi.Bus.SetCR2_FRXTH(1)
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}
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// Set baud rate for SPI
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func (spi *SPI) getBaudRate(config SPIConfig) uint32 {
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var conf uint32
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localFrequency := config.Frequency
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// Default
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if localFrequency == 0 {
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localFrequency = 4e6
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}
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// set frequency dependent on PCLK prescaler
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switch {
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case localFrequency < 250000:
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conf = stm32.SPI_CR1_BR_Div256
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case localFrequency < 500000:
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conf = stm32.SPI_CR1_BR_Div128
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case localFrequency < 1000000:
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conf = stm32.SPI_CR1_BR_Div64
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case localFrequency < 2000000:
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conf = stm32.SPI_CR1_BR_Div32
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case localFrequency < 4000000:
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conf = stm32.SPI_CR1_BR_Div16
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case localFrequency < 8000000:
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conf = stm32.SPI_CR1_BR_Div8
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case localFrequency < 16000000:
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conf = stm32.SPI_CR1_BR_Div4
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case localFrequency < 32000000:
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conf = stm32.SPI_CR1_BR_Div2
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default:
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// None of the specific baudrates were selected; choose the lowest speed
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conf = stm32.SPI_CR1_BR_Div256
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}
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return conf << stm32.SPI_CR1_BR_Pos
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}
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// Configure SPI pins for input output and clock
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func (spi *SPI) configurePins(config SPIConfig) {
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config.SCK.ConfigureAltFunc(PinConfig{Mode: PinModeSPICLK}, spi.AltFuncSelector)
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config.SDO.ConfigureAltFunc(PinConfig{Mode: PinModeSPISDO}, spi.AltFuncSelector)
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config.SDI.ConfigureAltFunc(PinConfig{Mode: PinModeSPISDI}, spi.AltFuncSelector)
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}
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//---------- I2C related types and code
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// Gets the value for TIMINGR register
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func (i2c *I2C) getFreqRange(br uint32) uint32 {
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// These are 'magic' values calculated by STM32CubeMX
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// for 64MHz PCLK1 (PLL: HSI16 / 1 * 8 / 2).
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// TODO: Do calculations based on PCLK1
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switch br {
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case 10 * KHz:
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return 0xF010F3FE // 64MHz, 10kHz I2C
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case 100 * KHz:
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return 0x30A0A7FB // 64MHz, 100kHz I2C (Standard mode)
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case 400 * KHz:
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return 0x10802D9B // 64MHz, 400kHz I2C (Fast mode)
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case 500 * KHz:
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return 0x00802172 // 64MHz, 500kHz I2C
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default:
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return 0
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}
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}
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// Enable peripheral clock
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func enableAltFuncClock(bus unsafe.Pointer) {
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switch bus {
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case unsafe.Pointer(stm32.PWR): // Power interface clock enable
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stm32.RCC.SetAPBENR1_PWREN(1)
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case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable
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stm32.RCC.SetAPBENR1_I2C1EN(1)
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case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable
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stm32.RCC.SetAPBENR1_I2C2EN(1)
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case unsafe.Pointer(stm32.USART2): // USART2 clock enable
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stm32.RCC.SetAPBENR1_USART2EN(1)
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case unsafe.Pointer(stm32.USART3): // USART3 clock enable
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stm32.RCC.SetAPBENR1_USART3EN(1)
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case unsafe.Pointer(stm32.USART4): // USART4 clock enable
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stm32.RCC.SetAPBENR1_USART4EN(1)
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case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable
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stm32.RCC.SetAPBENR1_SPI2EN(1)
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case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable
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stm32.RCC.SetAPBENR1_WWDGEN(1)
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case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable
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stm32.RCC.SetAPBENR1_TIM2EN(1)
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case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable
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stm32.RCC.SetAPBENR1_TIM3EN(1)
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case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable
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stm32.RCC.SetAPBENR1_TIM6EN(1)
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case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable
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stm32.RCC.SetAPBENR1_TIM7EN(1)
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case unsafe.Pointer(stm32.LPUART1): // LPUART1 clock enable
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stm32.RCC.SetAPBENR1_LPUART1EN(1)
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case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable
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stm32.RCC.SetAPBENR2_TIM1EN(1)
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case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable
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stm32.RCC.SetAPBENR2_SPI1EN(1)
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case unsafe.Pointer(stm32.USART1): // USART1 clock enable
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stm32.RCC.SetAPBENR2_USART1EN(1)
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case unsafe.Pointer(stm32.TIM14): // TIM14 clock enable
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stm32.RCC.SetAPBENR2_TIM14EN(1)
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case unsafe.Pointer(stm32.TIM15): // TIM15 clock enable
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stm32.RCC.SetAPBENR2_TIM15EN(1)
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case unsafe.Pointer(stm32.TIM16): // TIM16 clock enable
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stm32.RCC.SetAPBENR2_TIM16EN(1)
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case unsafe.Pointer(stm32.TIM17): // TIM17 clock enable
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stm32.RCC.SetAPBENR2_TIM17EN(1)
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case unsafe.Pointer(stm32.ADC): // ADC clock enable
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stm32.RCC.SetAPBENR2_ADCEN(1)
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case unsafe.Pointer(stm32.FDCAN1), unsafe.Pointer(stm32.FDCAN2): // FDCAN clock enable
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stm32.RCC.SetAPBENR1_FDCANEN(1)
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}
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}
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//---------- Timer related code
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// Alternate function constants for STM32G0
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const (
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AF0_SYSTEM = 0
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AF1_TIM1_TIM2_TIM3_LPTIM1 = 1
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AF2_TIM1_TIM2_TIM3_TIM14_I2C2 = 2
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AF3_USART5_USART6_LPUART2 = 3
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AF3_FDCAN1_FDCAN2 = 3 // FDCAN on PC2/PC3/PC4/PC5, PD12/PD13/PD14/PD15
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AF4_USART1_USART2_TIM14 = 4
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AF5_SPI1_SPI2_TIM16_TIM17 = 5
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AF6_SPI2_USART3_USART4_I2C1 = 6
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AF7_USART1_USART2_COMP1_COMP2 = 7
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AF8_I2C1_I2C2_UCPD1_UCPD2 = 8
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AF9_SPI2_TIM14_TIM15 = 9
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AF9_FDCAN1_FDCAN2 = 9 // FDCAN on PA11/PA12, PB8/PB9
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)
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var (
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TIM1 = TIM{
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EnableRegister: &stm32.RCC.APBENR2,
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EnableFlag: stm32.RCC_APBENR2_TIM1EN,
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Device: stm32.TIM1,
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Channels: [4]TimerChannel{
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{Pins: []PinFunction{{PA8, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}}},
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{Pins: []PinFunction{{PA9, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}}},
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{Pins: []PinFunction{{PA10, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}}},
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{Pins: []PinFunction{{PA11, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}}},
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},
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busFreq: APB2_TIM_FREQ,
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}
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TIM2 = TIM{
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EnableRegister: &stm32.RCC.APBENR1,
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EnableFlag: stm32.RCC_APBENR1_TIM2EN,
|
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Device: stm32.TIM2,
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Channels: [4]TimerChannel{
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{Pins: []PinFunction{{PA0, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}, {PA5, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}, {PA15, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}}},
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{Pins: []PinFunction{{PA1, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}, {PB3, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}}},
|
||||
{Pins: []PinFunction{{PA2, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}, {PB10, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}}},
|
||||
{Pins: []PinFunction{{PA3, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}, {PB11, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}}},
|
||||
},
|
||||
busFreq: APB1_TIM_FREQ,
|
||||
}
|
||||
|
||||
TIM3 = TIM{
|
||||
EnableRegister: &stm32.RCC.APBENR1,
|
||||
EnableFlag: stm32.RCC_APBENR1_TIM3EN,
|
||||
Device: stm32.TIM3,
|
||||
Channels: [4]TimerChannel{
|
||||
{Pins: []PinFunction{{PA6, AF1_TIM1_TIM2_TIM3_LPTIM1}, {PB4, AF1_TIM1_TIM2_TIM3_LPTIM1}, {PC6, AF1_TIM1_TIM2_TIM3_LPTIM1}}},
|
||||
{Pins: []PinFunction{{PA7, AF1_TIM1_TIM2_TIM3_LPTIM1}, {PB5, AF1_TIM1_TIM2_TIM3_LPTIM1}, {PC7, AF1_TIM1_TIM2_TIM3_LPTIM1}}},
|
||||
{Pins: []PinFunction{{PB0, AF1_TIM1_TIM2_TIM3_LPTIM1}, {PC8, AF1_TIM1_TIM2_TIM3_LPTIM1}}},
|
||||
{Pins: []PinFunction{{PB1, AF1_TIM1_TIM2_TIM3_LPTIM1}, {PC9, AF1_TIM1_TIM2_TIM3_LPTIM1}}},
|
||||
},
|
||||
busFreq: APB1_TIM_FREQ,
|
||||
}
|
||||
|
||||
TIM6 = TIM{
|
||||
EnableRegister: &stm32.RCC.APBENR1,
|
||||
EnableFlag: stm32.RCC_APBENR1_TIM6EN,
|
||||
Device: stm32.TIM6,
|
||||
Channels: [4]TimerChannel{
|
||||
{Pins: []PinFunction{}},
|
||||
{Pins: []PinFunction{}},
|
||||
{Pins: []PinFunction{}},
|
||||
{Pins: []PinFunction{}},
|
||||
},
|
||||
busFreq: APB1_TIM_FREQ,
|
||||
}
|
||||
|
||||
TIM7 = TIM{
|
||||
EnableRegister: &stm32.RCC.APBENR1,
|
||||
EnableFlag: stm32.RCC_APBENR1_TIM7EN,
|
||||
Device: stm32.TIM7,
|
||||
Channels: [4]TimerChannel{
|
||||
{Pins: []PinFunction{}},
|
||||
{Pins: []PinFunction{}},
|
||||
{Pins: []PinFunction{}},
|
||||
{Pins: []PinFunction{}},
|
||||
},
|
||||
busFreq: APB1_TIM_FREQ,
|
||||
}
|
||||
|
||||
TIM14 = TIM{
|
||||
EnableRegister: &stm32.RCC.APBENR2,
|
||||
EnableFlag: stm32.RCC_APBENR2_TIM14EN,
|
||||
Device: stm32.TIM14,
|
||||
Channels: [4]TimerChannel{
|
||||
{Pins: []PinFunction{{PA4, AF4_USART1_USART2_TIM14}, {PA7, AF4_USART1_USART2_TIM14}, {PB1, AF0_SYSTEM}}},
|
||||
{Pins: []PinFunction{}},
|
||||
{Pins: []PinFunction{}},
|
||||
{Pins: []PinFunction{}},
|
||||
},
|
||||
busFreq: APB2_TIM_FREQ,
|
||||
}
|
||||
|
||||
TIM15 = TIM{
|
||||
EnableRegister: &stm32.RCC.APBENR2,
|
||||
EnableFlag: stm32.RCC_APBENR2_TIM15EN,
|
||||
Device: stm32.TIM15,
|
||||
Channels: [4]TimerChannel{
|
||||
{Pins: []PinFunction{{PA2, AF5_SPI1_SPI2_TIM16_TIM17}, {PB14, AF5_SPI1_SPI2_TIM16_TIM17}}},
|
||||
{Pins: []PinFunction{{PA3, AF5_SPI1_SPI2_TIM16_TIM17}, {PB15, AF5_SPI1_SPI2_TIM16_TIM17}}},
|
||||
{Pins: []PinFunction{}},
|
||||
{Pins: []PinFunction{}},
|
||||
},
|
||||
busFreq: APB2_TIM_FREQ,
|
||||
}
|
||||
|
||||
TIM16 = TIM{
|
||||
EnableRegister: &stm32.RCC.APBENR2,
|
||||
EnableFlag: stm32.RCC_APBENR2_TIM16EN,
|
||||
Device: stm32.TIM16,
|
||||
Channels: [4]TimerChannel{
|
||||
{Pins: []PinFunction{{PA6, AF5_SPI1_SPI2_TIM16_TIM17}, {PB8, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}}},
|
||||
{Pins: []PinFunction{}},
|
||||
{Pins: []PinFunction{}},
|
||||
{Pins: []PinFunction{}},
|
||||
},
|
||||
busFreq: APB2_TIM_FREQ,
|
||||
}
|
||||
|
||||
TIM17 = TIM{
|
||||
EnableRegister: &stm32.RCC.APBENR2,
|
||||
EnableFlag: stm32.RCC_APBENR2_TIM17EN,
|
||||
Device: stm32.TIM17,
|
||||
Channels: [4]TimerChannel{
|
||||
{Pins: []PinFunction{{PA7, AF5_SPI1_SPI2_TIM16_TIM17}, {PB9, AF2_TIM1_TIM2_TIM3_TIM14_I2C2}}},
|
||||
{Pins: []PinFunction{}},
|
||||
{Pins: []PinFunction{}},
|
||||
{Pins: []PinFunction{}},
|
||||
},
|
||||
busFreq: APB2_TIM_FREQ,
|
||||
}
|
||||
)
|
||||
|
||||
func (t *TIM) registerUPInterrupt() interrupt.Interrupt {
|
||||
switch t {
|
||||
case &TIM1:
|
||||
return interrupt.New(stm32.IRQ_TIM1_BRK_UP_TRG_COM, TIM1.handleUPInterrupt)
|
||||
case &TIM2:
|
||||
return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt)
|
||||
case &TIM3:
|
||||
return interrupt.New(stm32.IRQ_TIM3_TIM4, TIM3.handleUPInterrupt)
|
||||
case &TIM6:
|
||||
return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleUPInterrupt)
|
||||
case &TIM7:
|
||||
return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt)
|
||||
case &TIM14:
|
||||
return interrupt.New(stm32.IRQ_TIM14, TIM14.handleUPInterrupt)
|
||||
case &TIM15:
|
||||
return interrupt.New(stm32.IRQ_TIM15, TIM15.handleUPInterrupt)
|
||||
case &TIM16:
|
||||
return interrupt.New(stm32.IRQ_TIM16, TIM16.handleUPInterrupt)
|
||||
case &TIM17:
|
||||
return interrupt.New(stm32.IRQ_TIM17, TIM17.handleUPInterrupt)
|
||||
}
|
||||
|
||||
return interrupt.Interrupt{}
|
||||
}
|
||||
|
||||
func (t *TIM) registerOCInterrupt() interrupt.Interrupt {
|
||||
switch t {
|
||||
case &TIM1:
|
||||
return interrupt.New(stm32.IRQ_TIM1_CC, TIM1.handleOCInterrupt)
|
||||
case &TIM2:
|
||||
return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt)
|
||||
case &TIM3:
|
||||
return interrupt.New(stm32.IRQ_TIM3_TIM4, TIM3.handleOCInterrupt)
|
||||
case &TIM6:
|
||||
return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleOCInterrupt)
|
||||
case &TIM7:
|
||||
return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt)
|
||||
case &TIM14:
|
||||
return interrupt.New(stm32.IRQ_TIM14, TIM14.handleOCInterrupt)
|
||||
case &TIM15:
|
||||
return interrupt.New(stm32.IRQ_TIM15, TIM15.handleOCInterrupt)
|
||||
case &TIM16:
|
||||
return interrupt.New(stm32.IRQ_TIM16, TIM16.handleOCInterrupt)
|
||||
case &TIM17:
|
||||
return interrupt.New(stm32.IRQ_TIM17, TIM17.handleOCInterrupt)
|
||||
}
|
||||
|
||||
return interrupt.Interrupt{}
|
||||
}
|
||||
|
||||
func (t *TIM) enableMainOutput() {
|
||||
t.Device.SetBDTR_MOE(1)
|
||||
}
|
||||
|
||||
type arrtype = uint32
|
||||
type arrRegType = volatile.Register32
|
||||
|
||||
const (
|
||||
ARR_MAX = 0x10000
|
||||
PSC_MAX = 0x10000
|
||||
)
|
||||
|
||||
func initRNG() {
|
||||
// STM32G0B1 does not have a hardware RNG peripheral
|
||||
// RNG is available on some other STM32G0 variants
|
||||
}
|
||||
Reference in New Issue
Block a user