riscv: add bare-bones interrupt support

This commit adds support for timer interrupts, replacing the busy loop
that was used before. It is perhaps the most simple interrupt to
implement and should serve as the basis for further interrupt support in
RISC-V.

targets/riscv.ld

@@ -2,7 +2,10 @@ SECTIONS
 {
     .text :
     {
+        . = ALIGN(4);
         KEEP(*(.init))
+        . = ALIGN(4);
+        *(.text.handleInterruptASM)
         *(.text)
         *(.text.*)
         *(.rodata)