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fe310: add support for bit banging drivers

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This is necessary to add support for WS2812.
This commit is contained in:
Ayke van Laethem
2021-10-20 02:23:59 +02:00
committed by Ron Evans
parent 3f89fa0bee
commit b5b2600b7b
1 changed files with 16 additions and 0 deletions
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src/machine/machine_fe310.go
+16
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@@ -50,6 +50,22 @@ func (p Pin) Get() bool {
return (val > 0) return (val > 0)
} }
// Return the register and mask to enable a given GPIO pin. This can be used to
// implement bit-banged drivers.
//
// Warning: only use this on an output pin!
func (p Pin) PortMaskSet() (*uint32, uint32) {
return (*uint32)(unsafe.Pointer(&sifive.GPIO0.PORT)), sifive.GPIO0.PORT.Get() | (1 << uint8(p))
}
// Return the register and mask to disable a given GPIO pin. This can be used to
// implement bit-banged drivers.
//
// Warning: only use this on an output pin!
func (p Pin) PortMaskClear() (*uint32, uint32) {
return (*uint32)(unsafe.Pointer(&sifive.GPIO0.PORT)), sifive.GPIO0.PORT.Get() &^ (1 << uint8(p))
}
type UART struct { type UART struct {
Bus *sifive.UART_Type Bus *sifive.UART_Type
Buffer *RingBuffer Buffer *RingBuffer