Puya PY32F MCU support (#5106)

* pinout yamls removed

* machine: implement default UART pin configuration for Embedfire boards

* flash command moved to chip level so VS Code plugin can select bare chip

* machine: add support for alternate pin mode configuration

* add build targets for embedfire on py32

* add support for embedfire target in GNUmakefile for py32

* lib/py32-svd: remove duplicate DBGMCU.IDCODE CODE field

Update submodule to fix duplicate SetIDCODE/GetIDCODE method
declarations in the generated py32f002bxx.go device file.

* update subproject commit reference in py32-svd

* refactor: update CPU frequency handling in machine and runtime packages

* refactor: replace ConfigureUARTPin function with direct pin configuration in UART setup

* SetAltFunc documentation for GPIO pin alternate functions

* refactor: improve UART write and flush error handling with timeout

* machine/py32: generalize UART driver to any USART

Add a per-instance setup func to the UART type so the driver is no longer
hardwired to USART1. DefaultUART stays USART1; add UART2 (USART2) in a
separately build-tagged file since py32f002x parts lack USART2. RX IRQ
handlers reference runtime-assigned vars to break the init cycle, and setup
is assigned in the var initializer so it runs before InitSerial.

Add the py32f003_32k_4k target (32K flash / 4K RAM).

* Add canonical PY32F002, F003, and F030 density targets

Use CMSIS/pyocd device names for target files and build tags. Add all F003 and F030 densities plus F002A/B, correct F002B to 24K flash and its own startup file, fix the F030x8 pyocd target, and update Embedfire inheritance.

* Add targets for all PY32 CMSIS devices

* Support all PY32 register layout variants

* machine/py32: use generated register definitions

* machine/py32: fix alternate-function documentation

* machine/py32: report the configured CPU frequency

* machine/py32: use unsafe.Add for GPIO ports

* machine/py32: bound and yield UART polling

* machine/py32: configure UART pins from UARTConfig

* build: use the current PY32 SVD repository URL

* test: cover PY32 UART register layouts

* machine/py32: restore dynamic CPU frequency tracking

* machine/py32: share the USART TX-ready bit

* targets/py32: scale system stacks with RAM

* machine/py32: keep clock state internal

* targets/py32: normalize generated metadata

* machine/py32: normalize GPIO configuration

* machine/py32: fix T020 UART setup

* machine/py32: reduce clock variant files

* machine/py32: clean up UART variants

* machine/py32: decouple UART clock capability

* lib/py32-svd: use organization repository

* runtime/py32: name 24MHz HSI encodings

* machine/py32: derive startup clock from capability

* machine/py32: use generated USART clock mask

* machine/py32: name T020 8-bit UART mode

* ci: include PY32 in sharded smoke tests

* runtime: remove PY32 HSI frequency workaround

tools/gen-py32-targets/README.md

@@ -0,0 +1,59 @@
+# PY32 target generator
+
+This command generates TinyGo target JSON and linker scripts for Puya PY32
+microcontrollers. Run it from the repository root:
+
+```sh
+make gen-target-py32
+```
+
+The normalized [device table](devices.csv) was derived from the `<device>` and
+`<variant>` leaves in the official Puya CMSIS-Pack PDSC files. Memory values are
+the inherited default `IROM1` and `IRAM1` regions. The three PY32E407 parts have
+multiple adjacent default RAM regions; their linker definitions combine those
+regions into one contiguous RAM range.
+
+The table contains 87 concrete devices associated with 40 SVD families. The
+pack also supplies `PY32F001xx.svd` without a corresponding PDSC device, so the
+generator creates its family target but cannot create a concrete memory target.
+Together these inputs produce family targets for all 41 available SVDs.
+
+Cortex-M0+ families inherit `py32`; PY32E407, PY32F403, and PY32F410 families
+inherit `py32-m4`, which uses TinyGo's standard soft-float Cortex-M4 ABI. Targets
+whose SVD has no `GPIO.AFRH` register receive the `py32_no_gpio_afrh` build tag.
+
+Puya's SVDs are inconsistent about GPIO `groupName`: some describe identical
+ports as `GPIOA_Type`, `GPIOB_Type`, and so on, while others use one
+`GPIO_Type`. The `py32-svd` updater validates the register structures and
+patches the published SVDs to use the common `GPIO` group. This is a correction
+to the vendor metadata, not a target capability, so neither TinyGo's generic
+SVD generator nor the target build tags need PY32-specific handling for it.
+
+Real register-layout differences are selected by generated capability tags.
+These cover the `OSPEEDR`/`OSPDDER` GPIO spelling, RCC GPIO and UART clock
+registers, `USART` versus `UART` blocks, split USART receive/transmit data
+registers, and HSI selector availability. Keep these classifications in the
+target generator rather than adding long family expressions to machine files.
+
+All concrete target JSON files and linker scripts are generated so inheritance,
+memory definitions, and stack sizes remain consistent. Verified flashing
+commands are preserved in the generator; other targets omit them until a
+compatible programmer identifier is known.
+
+The system and interrupt stack is sized from available RAM: targets with up to
+4 KiB use 1 KiB, targets with up to 16 KiB use 2 KiB, and larger targets use
+4 KiB. This linker-defined stack is distinct from goroutine fallback stacks
+selected by TinyGo's `--stack-size` option.
+
+## Machine support status
+
+A minimal program compiles for all 87 concrete targets. GPIO, RCC, runtime
+clock setup, and the default serial block are selected according to each SVD's
+register layout. This is compile-time coverage, not hardware validation for
+every device. In particular, PY32F410 SVD interrupt metadata stops before the
+serial interrupts, so its default USART is configured without receive
+interrupts rather than assigning an unverified IRQ number. The M4 SVDs also do
+not expose the M0+ `ICSCR.HSI_FS` selector, so the runtime preserves their reset
+clock configuration and initially reports the vendor-defined 8 MHz reset
+frequency. Custom clock HALs must update TinyGo's internal clock state, then
+reconfigure SysTick and frequency-dependent peripherals.