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https://github.com/tinygo-org/tinygo.git
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add support for GPIO interrupts on esp32c3
Update interrupt_esp32c3.go: make callHandler inline save and restore MSTATUS along with MEPC save and restore actual threshold value and call fence print additional data during exception
This commit is contained in:
Dmitriy
Ron Evans
@@ -34,9 +34,9 @@ func (i Interrupt) Enable() error {
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// Set pulse interrupt type (rising edge detection)
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esp.INTERRUPT_CORE0.CPU_INT_TYPE.SetBits(1 << i.num)
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// Set default threshold to 5
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// Set default threshold to defaultThreshold
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reg := (*volatile.Register32)(unsafe.Pointer((uintptr(unsafe.Pointer(&esp.INTERRUPT_CORE0.CPU_INT_PRI_0)) + uintptr(i.num)*4)))
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reg.Set(5)
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reg.Set(defaultThreshold)
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// Reset interrupt before reenabling
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esp.INTERRUPT_CORE0.CPU_INT_CLEAR.SetBits(1 << i.num)
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@@ -47,6 +47,118 @@ func (i Interrupt) Enable() error {
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return nil
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}
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// Adding pseudo function calls that is replaced by the compiler with the actual
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// functions registered through interrupt.New.
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//go:linkname callHandlers runtime/interrupt.callHandlers
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func callHandlers(num int)
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const (
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IRQNUM_1 = 1 + iota
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IRQNUM_2
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IRQNUM_3
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IRQNUM_4
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IRQNUM_5
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IRQNUM_6
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IRQNUM_7
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IRQNUM_8
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IRQNUM_9
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IRQNUM_10
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IRQNUM_11
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IRQNUM_12
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IRQNUM_13
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IRQNUM_14
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IRQNUM_15
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IRQNUM_16
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IRQNUM_17
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IRQNUM_18
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IRQNUM_19
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IRQNUM_20
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IRQNUM_21
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IRQNUM_22
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IRQNUM_23
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IRQNUM_24
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IRQNUM_25
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IRQNUM_26
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IRQNUM_27
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IRQNUM_28
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IRQNUM_29
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IRQNUM_30
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IRQNUM_31
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)
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const (
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defaultThreshold = 5
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disableThreshold = 10
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)
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//go:inline
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func callHandler(n int) {
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switch n {
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case IRQNUM_1:
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callHandlers(IRQNUM_1)
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case IRQNUM_2:
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callHandlers(IRQNUM_2)
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case IRQNUM_3:
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callHandlers(IRQNUM_3)
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case IRQNUM_4:
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callHandlers(IRQNUM_4)
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case IRQNUM_5:
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callHandlers(IRQNUM_5)
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case IRQNUM_6:
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callHandlers(IRQNUM_6)
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case IRQNUM_7:
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callHandlers(IRQNUM_7)
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case IRQNUM_8:
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callHandlers(IRQNUM_8)
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case IRQNUM_9:
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callHandlers(IRQNUM_9)
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case IRQNUM_10:
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callHandlers(IRQNUM_10)
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case IRQNUM_11:
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callHandlers(IRQNUM_11)
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case IRQNUM_12:
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callHandlers(IRQNUM_12)
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case IRQNUM_13:
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callHandlers(IRQNUM_13)
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case IRQNUM_14:
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callHandlers(IRQNUM_14)
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case IRQNUM_15:
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callHandlers(IRQNUM_15)
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case IRQNUM_16:
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callHandlers(IRQNUM_16)
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case IRQNUM_17:
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callHandlers(IRQNUM_17)
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case IRQNUM_18:
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callHandlers(IRQNUM_18)
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case IRQNUM_19:
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callHandlers(IRQNUM_19)
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case IRQNUM_20:
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callHandlers(IRQNUM_20)
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case IRQNUM_21:
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callHandlers(IRQNUM_21)
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case IRQNUM_22:
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callHandlers(IRQNUM_22)
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case IRQNUM_23:
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callHandlers(IRQNUM_23)
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case IRQNUM_24:
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callHandlers(IRQNUM_24)
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case IRQNUM_25:
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callHandlers(IRQNUM_25)
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case IRQNUM_26:
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callHandlers(IRQNUM_26)
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case IRQNUM_27:
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callHandlers(IRQNUM_27)
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case IRQNUM_28:
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callHandlers(IRQNUM_28)
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case IRQNUM_29:
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callHandlers(IRQNUM_29)
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case IRQNUM_30:
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callHandlers(IRQNUM_30)
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case IRQNUM_31:
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callHandlers(IRQNUM_31)
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}
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}
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//export handleInterrupt
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func handleInterrupt() {
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mcause := riscv.MCAUSE.Get()
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@@ -54,12 +166,17 @@ func handleInterrupt() {
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interruptNumber := uint32(mcause & 0x1f)
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if !exception && interruptNumber > 0 {
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// save mepc, which could be overwritten by another CPU interrupt
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// save MSTATUS & MEPC, which could be overwritten by another CPU interrupt
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mstatus := riscv.MSTATUS.Get()
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mepc := riscv.MEPC.Get()
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// Useing threshold to temporary disable this interrupts.
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// FYI: using CPU interrupt enable bit make runtime to loose interrupts.
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reg := (*volatile.Register32)(unsafe.Pointer((uintptr(unsafe.Pointer(&esp.INTERRUPT_CORE0.CPU_INT_PRI_0)) + uintptr(interruptNumber)*4)))
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thresholdSave := reg.Get()
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reg.Set(disableThreshold)
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riscv.Asm("fence")
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// disable interrupt
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interruptBit := uint32(1 << interruptNumber)
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esp.INTERRUPT_CORE0.CPU_INT_ENABLE.ClearBits(interruptBit)
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// reset pending status interrupt
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if esp.INTERRUPT_CORE0.CPU_INT_TYPE.Get()&interruptBit != 0 {
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@@ -72,23 +189,22 @@ func handleInterrupt() {
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}
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// enable CPU interrupts
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riscv.MSTATUS.SetBits(0x8)
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riscv.MSTATUS.SetBits(1 << 3)
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// Call registered interrupt handler(s)
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esp.HandleInterrupt(int(interruptNumber))
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callHandler(int(interruptNumber))
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// disable CPU interrupts
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riscv.MSTATUS.ClearBits(0x8)
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riscv.MSTATUS.ClearBits(1 << 3)
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// mpie must be set to 1 to resume interrupts after 'MRET'
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riscv.MSTATUS.SetBits(0x80)
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// restore interrupt threshold to enable interrupt again
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reg.Set(thresholdSave)
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riscv.Asm("fence")
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// restore MEPC
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// restore MSTATUS & MEPC
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riscv.MSTATUS.Set(mstatus)
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riscv.MEPC.Set(mepc)
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// enable this interrupt
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esp.INTERRUPT_CORE0.CPU_INT_ENABLE.SetBits(interruptBit)
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// do not enable CPU interrupts now
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// the 'MRET' in src/device/riscv/handleinterrupt.S will copies the state of MPIE back into MIE, and subsequently clears MPIE.
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// riscv.MSTATUS.SetBits(0x8)
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@@ -104,6 +220,16 @@ func handleException(mcause uintptr) {
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println("*** Exception: pc:", riscv.MEPC.Get())
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println("*** Exception: code:", uint32(mcause&0x1f))
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println("*** Exception: mcause:", mcause)
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switch uint32(mcause & 0x1f) {
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case 1:
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println("*** virtual addess:", riscv.MTVAL.Get())
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case 2:
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println("*** opcode:", riscv.MTVAL.Get())
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case 5:
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println("*** read address:", riscv.MTVAL.Get())
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case 7:
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println("*** write address:", riscv.MTVAL.Get())
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}
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for {
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riscv.Asm("wfi")
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}
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