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nucleol552ze: implementation with CLOCK, LED, and UART
This commit is contained in:
Kenneth Bell
committed by
deadprogram
deadprogram
parent
801bd2a7ff
commit
af02c09b56
@@ -0,0 +1,243 @@
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// +build stm32,stm32l5x2
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package runtime
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import (
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"device/arm"
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"device/stm32"
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"machine"
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"runtime/interrupt"
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"runtime/volatile"
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)
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func init() {
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initCLK()
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initTIM15()
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machine.UART0.Configure(machine.UARTConfig{})
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initTIM16()
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}
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func putchar(c byte) {
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machine.UART0.WriteByte(c)
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}
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const (
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HSE_STARTUP_TIMEOUT = 0x0500
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PLL_M = 1
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PLL_N = 55
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PLL_P = 7 // RCC_PLLP_DIV7
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PLL_Q = 2 // RCC_PLLQ_DIV2
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PLL_R = 2 // RCC_PLLR_DIV2
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)
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/*
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clock settings
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+-------------+-----------+
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| LSE | 32.768khz |
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| SYSCLK | 110mhz |
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| HCLK | 110mhz |
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| APB1(PCLK1) | 110mhz |
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| APB2(PCLK2) | 110mhz |
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+-------------+-----------+
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*/
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func initCLK() {
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// PWR_CLK_ENABLE
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_PWREN)
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_ = stm32.RCC.APB1ENR1.Get()
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// PWR_VOLTAGESCALING_CONFIG
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stm32.PWR.CR1.ReplaceBits(0, stm32.PWR_CR1_VOS_Msk, 0)
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_ = stm32.PWR.CR1.Get()
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// Initialize the High-Speed External Oscillator
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initOsc()
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// Set flash wait states (min 5 latency units) based on clock
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if (stm32.FLASH.ACR.Get() & 0xF) < 5 {
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stm32.FLASH.ACR.ReplaceBits(5, 0xF, 0)
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}
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// Ensure HCLK does not exceed max during transition
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stm32.RCC.CFGR.ReplaceBits(8<<stm32.RCC_CFGR_HPRE_Pos, stm32.RCC_CFGR_HPRE_Msk, 0)
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// Set SYSCLK source and wait
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// (3 = RCC_SYSCLKSOURCE_PLLCLK, 2=RCC_CFGR_SWS_Pos)
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stm32.RCC.CFGR.ReplaceBits(3, stm32.RCC_CFGR_SW_Msk, 0)
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for stm32.RCC.CFGR.Get()&(3<<2) != (3 << 2) {
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}
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// Set HCLK
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// (0 = RCC_SYSCLKSOURCE_PLLCLK)
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stm32.RCC.CFGR.ReplaceBits(0, stm32.RCC_CFGR_HPRE_Msk, 0)
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// Set flash wait states (max 5 latency units) based on clock
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if (stm32.FLASH.ACR.Get() & 0xF) > 5 {
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stm32.FLASH.ACR.ReplaceBits(5, 0xF, 0)
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}
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// Set APB1 and APB2 clocks (0 = DIV1)
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stm32.RCC.CFGR.ReplaceBits(0, stm32.RCC_CFGR_PPRE1_Msk, 0)
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stm32.RCC.CFGR.ReplaceBits(0, stm32.RCC_CFGR_PPRE2_Msk, 0)
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}
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func initOsc() {
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// Enable HSI, wait until ready
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stm32.RCC.CR.SetBits(stm32.RCC_CR_HSION)
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for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSIRDY) {
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}
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// Disable Backup domain protection
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if !stm32.PWR.CR1.HasBits(stm32.PWR_CR1_DBP) {
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stm32.PWR.CR1.SetBits(stm32.PWR_CR1_DBP)
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for !stm32.PWR.CR1.HasBits(stm32.PWR_CR1_DBP) {
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}
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}
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// Set LSE Drive to LOW
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stm32.RCC.BDCR.ReplaceBits(0, stm32.RCC_BDCR_LSEDRV_Msk, 0)
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// Enable LSE, wait until ready
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stm32.RCC.BDCR.SetBits(stm32.RCC_BDCR_LSEON)
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for !stm32.RCC.BDCR.HasBits(stm32.RCC_BDCR_LSEON) {
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}
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// Ensure LSESYS disabled
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stm32.RCC.BDCR.ClearBits(stm32.RCC_BDCR_LSESYSEN)
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for stm32.RCC.BDCR.HasBits(stm32.RCC_BDCR_LSESYSEN) {
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}
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// Enable HSI48, wait until ready
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stm32.RCC.CRRCR.SetBits(stm32.RCC_CRRCR_HSI48ON)
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for !stm32.RCC.CRRCR.HasBits(stm32.RCC_CRRCR_HSI48ON) {
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}
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// Disable the PLL, wait until disabled
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stm32.RCC.CR.ClearBits(stm32.RCC_CR_PLLON)
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for stm32.RCC.CR.HasBits(stm32.RCC_CR_PLLRDY) {
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}
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// Configure the PLL
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stm32.RCC.PLLCFGR.ReplaceBits(
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(1)| // 1 = RCC_PLLSOURCE_MSI
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(PLL_M-1)<<stm32.RCC_PLLCFGR_PLLM_Pos|
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(PLL_N<<stm32.RCC_PLLCFGR_PLLN_Pos)|
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(((PLL_Q>>1)-1)<<stm32.RCC_PLLCFGR_PLLQ_Pos)|
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(((PLL_R>>1)-1)<<stm32.RCC_PLLCFGR_PLLR_Pos)|
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(PLL_P<<stm32.RCC_PLLCFGR_PLLPDIV_Pos),
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stm32.RCC_PLLCFGR_PLLSRC_Msk|stm32.RCC_PLLCFGR_PLLM_Msk|
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stm32.RCC_PLLCFGR_PLLN_Msk|stm32.RCC_PLLCFGR_PLLP_Msk|
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stm32.RCC_PLLCFGR_PLLR_Msk|stm32.RCC_PLLCFGR_PLLPDIV_Msk,
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0)
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// Enable the PLL and PLL System Clock Output, wait until ready
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stm32.RCC.CR.SetBits(stm32.RCC_CR_PLLON)
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stm32.RCC.PLLCFGR.SetBits(stm32.RCC_PLLCFGR_PLLREN) // = RCC_PLL_SYSCLK
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for !stm32.RCC.CR.HasBits(stm32.RCC_CR_PLLRDY) {
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}
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}
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var (
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// tick in milliseconds
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tickCount timeUnit
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)
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var timerWakeup volatile.Register8
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func ticksToNanoseconds(ticks timeUnit) int64 {
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return int64(ticks) * 1000
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}
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func nanosecondsToTicks(ns int64) timeUnit {
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return timeUnit(ns / 1000)
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}
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// Enable the TIM15 clock.(sleep count)
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func initTIM15() {
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM15EN)
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intr := interrupt.New(stm32.IRQ_TIM15, handleTIM15)
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intr.SetPriority(0xc3)
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intr.Enable()
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}
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// Enable the TIM16 clock.(tick count)
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func initTIM16() {
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM16EN)
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// CK_INT = APB1 = 110mhz
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stm32.TIM16.PSC.Set(110000000/10000 - 1) // 110mhz to 10khz(0.1ms)
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stm32.TIM16.ARR.Set(10 - 1) // interrupt per 1ms
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// Enable the hardware interrupt.
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stm32.TIM16.DIER.SetBits(stm32.TIM_DIER_UIE)
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// Enable the timer.
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stm32.TIM16.CR1.SetBits(stm32.TIM_CR1_CEN)
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intr := interrupt.New(stm32.IRQ_TIM16, handleTIM16)
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intr.SetPriority(0xc1)
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intr.Enable()
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}
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const asyncScheduler = false
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// sleepTicks should sleep for specific number of microseconds.
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func sleepTicks(d timeUnit) {
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timerSleep(uint32(d))
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}
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// number of ticks (microseconds) since start.
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func ticks() timeUnit {
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// milliseconds to microseconds
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return tickCount * 1000
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}
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// ticks are in microseconds
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func timerSleep(ticks uint32) {
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timerWakeup.Set(0)
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// CK_INT = APB1 = 110mhz
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// prescale counter down from 110mhz to 10khz aka 0.1 ms frequency.
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stm32.TIM15.PSC.Set(110000000/10000 - 1)
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// set duty aka duration
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arr := (ticks / 100) - 1 // convert from microseconds to 0.1 ms
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if arr == 0 {
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arr = 1 // avoid blocking
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}
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stm32.TIM15.ARR.Set(arr)
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// Enable the hardware interrupt.
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stm32.TIM15.DIER.SetBits(stm32.TIM_DIER_UIE)
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// Enable the timer.
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stm32.TIM15.CR1.SetBits(stm32.TIM_CR1_CEN)
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// wait till timer wakes up
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for timerWakeup.Get() == 0 {
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arm.Asm("wfi")
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}
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}
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func handleTIM15(interrupt.Interrupt) {
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if stm32.TIM15.SR.HasBits(stm32.TIM_SR_UIF) {
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// Disable the timer.
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stm32.TIM15.CR1.ClearBits(stm32.TIM_CR1_CEN)
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// clear the update flag
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stm32.TIM15.SR.ClearBits(stm32.TIM_SR_UIF)
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// timer was triggered
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timerWakeup.Set(1)
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}
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}
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func handleTIM16(interrupt.Interrupt) {
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if stm32.TIM16.SR.HasBits(stm32.TIM_SR_UIF) {
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// clear the update flag
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stm32.TIM16.SR.ClearBits(stm32.TIM_SR_UIF)
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tickCount++
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}
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}
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