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esp32s3: add flash XIP boot assembly with cache/MMU init
The ESP32-S3 ROM bootloader loads IRAM/DRAM into SRAM but does not configure the flash cache or MMU. Previously the target incorrectly reused the ESP32 boot assembly (esp32.S) which lacks flash XIP support. Add a dedicated esp32s3.S boot assembly that: - Sets up windowed-ABI registers, stack, and FPU - Disables all watchdog timers (RTC, TIMG0, TIMG1, Super WDT) - Configures VECBASE and clears PS.EXCM before any callx4 - Calls ROM functions to configure cache modes: rom_config_instruction_cache_mode (16KB, 8-way, 32B line) rom_config_data_cache_mode (32KB, 8-way, 32B line) - Initializes MMU, maps flash page 0 for IROM and DROM, clears bus-shut bits, and enables both caches - Jumps to runtime.main in IROM (flash) Update the linker script (esp32s3.ld) to place .text and .rodata in flash-mapped regions (IROM/DROM) with proper alignment for the MMU page size. Update esp32s3-interrupts.S with proper exception vector handlers. Point esp32s3.json at the new esp32s3.S instead of esp32.S. Signed-off-by: deadprogram <ron@hybridgroup.com>
This commit is contained in:
deadprogram
@@ -0,0 +1,317 @@
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// Startup code for the ESP32-S3 (Xtensa LX7, windowed ABI).
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//
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// The ROM bootloader loads IRAM/DRAM segments into SRAM but does NOT
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// configure flash cache/MMU. We must:
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// 1. Set up the windowed-ABI register file and stack pointer.
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// 2. Set VECBASE and clear PS.EXCM (needed for callx4 window overflows).
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// 3. Disable watchdog timers.
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// 4. Configure the flash cache and MMU so IROM/DROM are accessible.
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// 5. Jump to runtime.main (in IROM).
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//
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// Cache/MMU init sequence (from NuttX esp_loader.c / ESP-IDF bootloader / esp-hal):
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// Phase A — configure cache modes:
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// a. rom_config_instruction_cache_mode(16KB, 8-way, 32B)
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// b. rom_Cache_Suspend_DCache()
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// c. rom_config_data_cache_mode(32KB, 8-way, 32B)
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// d. Cache_Resume_DCache(0)
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// Phase B — map flash pages:
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// e. Disable caches
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// f. Cache_MMU_Init() — reset all MMU entries to invalid
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// g. Cache_Set_IDROM_MMU_Size() — set IROM/DROM entry split
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// h. Write MMU entries mapping flash page 0 for IROM and DROM
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// i. Clear bus-shut bits
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// j. Enable caches + isync
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#define PS_WOE 0x00040000
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// -----------------------------------------------------------------------
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// Boot entry point — placed in IRAM by the linker.
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// -----------------------------------------------------------------------
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.section .text.call_start_cpu0
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.literal_position
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.align 4
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.Lstack_top_addr:
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.long _stack_top
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.Lmain_addr:
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.long main
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.Lvector_table_addr:
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.long _vector_table
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// WDT register addresses
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.Lwdt_key:
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.long 0x50D83AA1
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.Lrtc_wdt_protect:
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.long 0x600080B0
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.Lrtc_wdt_config0:
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.long 0x60008098
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.Ltimg0_wdt_protect:
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.long 0x6001F064
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.Ltimg0_wdt_config0:
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.long 0x6001F048
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.Ltimg1_wdt_protect:
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.long 0x60020064
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.Ltimg1_wdt_config0:
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.long 0x60020048
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.Lswd_protect:
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.long 0x600080B8
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.Lswd_key:
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.long 0x8F1D312A
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.Lswd_conf:
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.long 0x600080B4
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.Lswd_disable:
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.long 0x40000000
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// ROM function addresses (from ESP-IDF esp32s3.rom.ld)
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.Lrom_config_icache:
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.long 0x40001a1c
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.Lrom_config_dcache:
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.long 0x40001a28
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.Lrom_suspend_dcache:
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.long 0x400018b4
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.LCache_Resume_DCache:
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.long 0x400018c0
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.LCache_Disable_ICache:
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.long 0x4000186c
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.LCache_Disable_DCache:
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.long 0x40001884
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.LCache_MMU_Init:
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.long 0x40001998
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.LCache_Set_IDROM_MMU_Size:
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.long 0x40001914
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.LCache_Enable_ICache:
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.long 0x40001878
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.LCache_Enable_DCache:
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.long 0x40001890
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// Cache/MMU register addresses
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.Lmmu_table_base:
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.long 0x600C5000
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.Licache_ctrl1_reg:
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.long 0x600C4064
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.Ldcache_ctrl1_reg:
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.long 0x600C4004
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.global call_start_cpu0
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call_start_cpu0:
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// ---- 1. Windowed-ABI register file setup ----
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// Disable WOE so we can safely manipulate WINDOWSTART.
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rsr.ps a2
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movi a3, ~(PS_WOE)
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and a2, a2, a3
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wsr.ps a2
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rsync
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// Set WINDOWSTART to 1 << WINDOWBASE (mark only current window as valid).
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rsr.windowbase a2
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ssl a2
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movi a2, 1
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sll a2, a2
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wsr.windowstart a2
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rsync
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// Load stack pointer.
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l32r a1, .Lstack_top_addr
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// Re-enable WOE.
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rsr.ps a2
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movi a3, PS_WOE
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or a2, a2, a3
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wsr.ps a2
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rsync
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// Enable FPU (coprocessor 0).
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movi a2, 1
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wsr.cpenable a2
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rsync
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// ---- 2. Disable all watchdog timers (IMMEDIATELY, before any delay) ----
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l32r a3, .Lwdt_key
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movi a4, 0
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// RTC WDT
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l32r a2, .Lrtc_wdt_protect
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memw
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s32i a3, a2, 0
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l32r a5, .Lrtc_wdt_config0
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memw
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s32i a4, a5, 0
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memw
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s32i a4, a2, 0
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// TIMG0 WDT
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l32r a2, .Ltimg0_wdt_protect
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memw
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s32i a3, a2, 0
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l32r a5, .Ltimg0_wdt_config0
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memw
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s32i a4, a5, 0
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memw
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s32i a4, a2, 0
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// TIMG1 WDT
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l32r a2, .Ltimg1_wdt_protect
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memw
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s32i a3, a2, 0
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l32r a5, .Ltimg1_wdt_config0
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memw
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s32i a4, a5, 0
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memw
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s32i a4, a2, 0
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// Super WDT
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l32r a2, .Lswd_protect
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l32r a3, .Lswd_key
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memw
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s32i a3, a2, 0
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l32r a5, .Lswd_conf
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l32r a6, .Lswd_disable
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memw
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s32i a6, a5, 0
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memw
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s32i a4, a2, 0
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// ---- 3. Set VECBASE and clear PS.EXCM ----
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// VECBASE must be set before any callx4 so that window overflow
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// exceptions (triggered by register window rotation) route to our
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// handlers in IRAM, not the ROM's default vectors.
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l32r a8, .Lvector_table_addr
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wsr.vecbase a8
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rsync
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// Clear PS.EXCM (bit 4) and PS.INTLEVEL (bits 0-3).
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// The ROM bootloader may leave EXCM=1; with EXCM set any callx4
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// window overflow would become a double exception.
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// Set PS.UM (bit 5) so level-1 exceptions route to User vector.
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rsr.ps a2
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movi a3, ~0x1F
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and a2, a2, a3
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movi a3, 0x20
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or a2, a2, a3
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wsr.ps a2
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rsync
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// ---- 4. Configure flash cache and MMU ----
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//
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// ROM function calls use callx4 (windowed ABI):
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// a4 = target address (overwritten with return addr by call mechanism)
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// a5 = stack pointer for callee (becomes callee's a1 via entry)
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// a6 = first argument (becomes callee's a2)
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// a7 = second argument (becomes callee's a3)
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// a8 = third argument (becomes callee's a4)
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// Registers a0-a3 are preserved across callx4; a4-a11 may be clobbered.
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// Phase A: Configure cache modes (required for cache hardware to function).
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// Without this, the cache doesn't know its size/associativity/line-size
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// and cannot service flash accesses.
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// 4a. Configure ICache mode: 16KB, 8-way, 32-byte line
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movi a6, 0x4000 // cache_size = 16KB
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movi a7, 8 // ways = 8
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movi a8, 32 // line_size = 32
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mov a5, a1
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l32r a4, .Lrom_config_icache
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callx4 a4
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// 4b. Suspend DCache before configuring it
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mov a5, a1
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l32r a4, .Lrom_suspend_dcache
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callx4 a4
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// 4c. Configure DCache mode: 32KB, 8-way, 32-byte line
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movi a6, 0x8000 // cache_size = 32KB
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movi a7, 8 // ways = 8
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movi a8, 32 // line_size = 32
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mov a5, a1
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l32r a4, .Lrom_config_dcache
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callx4 a4
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// 4d. Resume DCache
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movi a6, 0
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mov a5, a1
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l32r a4, .LCache_Resume_DCache
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callx4 a4
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// Phase B: Map flash pages into MMU.
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// 4e. Disable ICache
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mov a5, a1
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l32r a4, .LCache_Disable_ICache
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callx4 a4
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// 4f. Disable DCache
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mov a5, a1
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l32r a4, .LCache_Disable_DCache
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callx4 a4
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// 4g. Initialize MMU (resets all 512 entries to invalid = 0x4000)
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mov a5, a1
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l32r a4, .LCache_MMU_Init
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callx4 a4
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// 4h. Set IDROM MMU size: even 256/256 split.
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// Each entry is 4 bytes, so 256 entries = 0x400 bytes per region.
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movi a6, 0x400 // irom_mmu_size (256 entries × 4 bytes)
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movi a7, 0x400 // drom_mmu_size (256 entries × 4 bytes)
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mov a5, a1
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l32r a4, .LCache_Set_IDROM_MMU_Size
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callx4 a4
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// 4i. Write MMU entries: map flash page 0 for both IROM and DROM.
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// MMU table at 0x600C5000: entries 0-255 = ICache, 256-511 = DCache.
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// Entry value 0 = flash page 0, valid (SOC_MMU_VALID = 0).
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// Our .text (IROM, VMA 0x42000xxx) and .rodata (DROM, VMA 0x3C000xxx)
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// both reside in flash page 0 (first 64KB).
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l32r a8, .Lmmu_table_base // a8 = 0x600C5000
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movi a9, 0 // flash page 0
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s32i a9, a8, 0 // Entry 0: ICache VMA 0x42000000
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addmi a10, a8, 0x400 // a10 = 0x600C5400 (entry 256)
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s32i a9, a10, 0 // Entry 256: DCache VMA 0x3C000000
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memw
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// 4j. Clear bus-shut bits so core 0 can access ICache and DCache buses.
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l32r a8, .Licache_ctrl1_reg // 0x600C4064
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movi a9, 0
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s32i a9, a8, 0 // Clear all ICACHE_CTRL1 shut bits
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l32r a8, .Ldcache_ctrl1_reg // 0x600C4004
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s32i a9, a8, 0 // Clear all DCACHE_CTRL1 shut bits
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memw
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// 4k. Enable ICache (arg: autoload = 0)
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movi a6, 0
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mov a5, a1
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l32r a4, .LCache_Enable_ICache
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callx4 a4
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// 4l. Enable DCache (arg: autoload = 0)
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movi a6, 0
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mov a5, a1
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l32r a4, .LCache_Enable_DCache
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callx4 a4
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// Flush instruction pipeline so new cache/MMU config takes effect.
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isync
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// ---- 5. Jump to main (in IROM) ----
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// Re-clear PS.EXCM in case ROM calls changed processor state.
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rsr.ps a2
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movi a3, ~0x1F
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and a2, a2, a3
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movi a3, 0x20
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or a2, a2, a3
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wsr.ps a2
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rsync
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mov a5, a1
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l32r a4, .Lmain_addr
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callx4 a4
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// If main returns, loop forever.
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1: j 1b
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// -----------------------------------------------------------------------
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// tinygo_scanCurrentStack — tail-jump to tinygo_scanstack.
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// -----------------------------------------------------------------------
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.section .text.tinygo_scanCurrentStack
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.global tinygo_scanCurrentStack
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tinygo_scanCurrentStack:
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j tinygo_scanstack
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