all: add emulation support for Cortex-M3 with QEMU

targets/cortex-m.s

@@ -0,0 +1,61 @@
+// Generic Cortex-M interrupt vector.
+// This vector is used by the QEMU target.
+
+.syntax unified
+
+// This is a convenience function for QEMU semihosting support.
+// At some point, this should be replaced by inline assembly.
+.section .text.SemihostingCall
+.global  SemihostingCall
+.type    SemihostingCall, %function
+SemihostingCall:
+    bkpt 0xab
+    bx   lr
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+.section .isr_vector
+.global  __isr_vector
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler