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atsame51: add initial support for feather-m4-can
This commit is contained in:
sago35
Ron Evans
@@ -0,0 +1,142 @@
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// +build feather_m4_can
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package machine
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import (
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"device/sam"
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"runtime/interrupt"
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)
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// used to reset into bootloader
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const RESET_MAGIC_VALUE = 0xf01669ef
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// GPIO Pins
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const (
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D0 = PB17 // UART0 RX/PWM available
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D1 = PB16 // UART0 TX/PWM available
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D4 = PA14 // PWM available
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D5 = PA16 // PWM available
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D6 = PA18 // PWM available
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D7 = PB03 // neopixel power
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D8 = PB02 // built-in neopixel
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D9 = PA19 // PWM available
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D10 = PA20 // can be used for PWM or UART1 TX
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D11 = PA21 // can be used for PWM or UART1 RX
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D12 = PA22 // PWM available
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D13 = PA23 // PWM available
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D21 = PA13 // PWM available
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D22 = PA12 // PWM available
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D23 = PB22 // PWM available
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D24 = PB23 // PWM available
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D25 = PA17 // PWM available
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)
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// Analog pins
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const (
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A0 = PA02 // ADC/AIN[0]
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A1 = PA05 // ADC/AIN[2]
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A2 = PB08 // ADC/AIN[3]
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A3 = PB09 // ADC/AIN[4]
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A4 = PA04 // ADC/AIN[5]
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A5 = PA06 // ADC/AIN[10]
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)
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const (
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LED = D13
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NEOPIXELS = D8
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)
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// UART0 aka USBCDC pins
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const (
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USBCDC_DM_PIN = PA24
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USBCDC_DP_PIN = PA25
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)
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const (
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UART_TX_PIN = D1
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UART_RX_PIN = D0
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)
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const (
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UART2_TX_PIN = A4
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UART2_RX_PIN = A5
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)
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// I2C pins
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const (
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SDA_PIN = D22 // SDA: SERCOM2/PAD[0]
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SCL_PIN = D21 // SCL: SERCOM2/PAD[1]
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)
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// SPI pins
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const (
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SPI0_SCK_PIN = D25 // SCK: SERCOM1/PAD[1]
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SPI0_SDO_PIN = D24 // SDO: SERCOM1/PAD[3]
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SPI0_SDI_PIN = D23 // SDI: SERCOM1/PAD[2]
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)
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// CAN pins
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const (
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CAN0_TX = PA22
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CAN0_RX = PA23
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CAN1_STANDBY = PB12
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CAN1_TX = PB14
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CAN1_RX = PB15
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BOOST_EN = PB13 // power control of CAN1's TCAN1051HGV (H: enable)
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CAN_STANDBY = CAN1_STANDBY
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CAN_S = CAN1_STANDBY
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CAN_TX = CAN1_TX
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CAN_RX = CAN1_RX
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)
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// USB CDC identifiers
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const (
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usb_STRING_PRODUCT = "Adafruit Feather M4 CAN"
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usb_STRING_MANUFACTURER = "Adafruit"
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)
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var (
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usb_VID uint16 = 0x239A
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usb_PID uint16 = 0x80CD
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)
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var (
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UART1 = UART{
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Buffer: NewRingBuffer(),
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Bus: sam.SERCOM5_USART_INT,
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SERCOM: 5,
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}
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UART2 = UART{
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Buffer: NewRingBuffer(),
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Bus: sam.SERCOM0_USART_INT,
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SERCOM: 0,
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}
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)
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func init() {
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UART1.Interrupt = interrupt.New(sam.IRQ_SERCOM5_2, UART1.handleInterrupt)
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UART2.Interrupt = interrupt.New(sam.IRQ_SERCOM0_2, UART2.handleInterrupt)
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// turn on neopixel
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D7.Configure(PinConfig{Mode: PinOutput})
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D7.High()
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}
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// I2C on the Feather M4.
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var (
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I2C0 = &I2C{
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Bus: sam.SERCOM2_I2CM,
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SERCOM: 2,
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}
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)
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// SPI on the Feather M4.
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var (
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SPI0 = SPI{
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Bus: sam.SERCOM1_SPIM,
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SERCOM: 1,
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}
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)
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@@ -0,0 +1,59 @@
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// +build sam,atsame51,atsame51j19
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// Peripheral abstraction layer for the atsame51.
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//
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// Datasheet:
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// http://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf
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//
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package machine
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import "device/sam"
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const HSRAM_SIZE = 0x00030000
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// This chip has five TCC peripherals, which have PWM as one feature.
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var (
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TCC0 = (*TCC)(sam.TCC0)
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TCC1 = (*TCC)(sam.TCC1)
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TCC2 = (*TCC)(sam.TCC2)
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TCC3 = (*TCC)(sam.TCC3)
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TCC4 = (*TCC)(sam.TCC4)
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)
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func (tcc *TCC) configureClock() {
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// Turn on timer clocks used for the TCC and use generic clock generator 0.
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switch tcc.timer() {
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case sam.TCC0:
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sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC0_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC0].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN)
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case sam.TCC1:
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sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_TCC1_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC1].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN)
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case sam.TCC2:
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sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC2_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC2].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN)
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case sam.TCC3:
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sam.MCLK.APBCMASK.SetBits(sam.MCLK_APBCMASK_TCC3_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC3].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN)
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case sam.TCC4:
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sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_TCC4_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_TCC4].Set((sam.GCLK_PCHCTRL_GEN_GCLK0 << sam.GCLK_PCHCTRL_GEN_Pos) | sam.GCLK_PCHCTRL_CHEN)
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}
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}
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func (tcc *TCC) timerNum() uint8 {
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switch tcc.timer() {
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case sam.TCC0:
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return 0
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case sam.TCC1:
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return 1
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case sam.TCC2:
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return 2
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case sam.TCC3:
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return 3
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case sam.TCC4:
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return 4
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default:
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return 0x0f // should not happen
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}
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}
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@@ -0,0 +1,43 @@
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// +build sam,atsame51,atsame51j19
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package runtime
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import (
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"device/sam"
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)
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func initSERCOMClocks() {
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// Turn on clock to SERCOM0 for UART0
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sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM0_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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// sets the "slow" clock shared by all SERCOM
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOMX_SLOW].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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// Turn on clock to SERCOM1
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sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM1_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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// Turn on clock to SERCOM2
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sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM2_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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// Turn on clock to SERCOM3
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sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM3_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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// Turn on clock to SERCOM4
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sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM4_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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// Turn on clock to SERCOM5
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sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM5_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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}
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