From 88a68eaf7e23a1ef334ed8560fae01d69f4fc75b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Teichgr=C3=A4ber?= Date: Mon, 23 Feb 2026 17:01:16 +0100 Subject: [PATCH] machine: stm32l0x1,l0x2: TIM: adapt to 32-bit register access Recent changes in stm32-svd result in a change from previous 16-bit register access to 32-bit access. Both access types are allowed, according to the register manuals. --- src/machine/machine_stm32l0x1.go | 4 ++-- src/machine/machine_stm32l0x2.go | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/machine/machine_stm32l0x1.go b/src/machine/machine_stm32l0x1.go index f0d23ca49..292b81f46 100644 --- a/src/machine/machine_stm32l0x1.go +++ b/src/machine/machine_stm32l0x1.go @@ -188,8 +188,8 @@ func (t *TIM) enableMainOutput() { // nothing to do - no BDTR register } -type arrtype = uint16 -type arrRegType = volatile.Register16 +type arrtype = uint32 +type arrRegType = volatile.Register32 const ( ARR_MAX = 0x10000 diff --git a/src/machine/machine_stm32l0x2.go b/src/machine/machine_stm32l0x2.go index 2a747920b..fe1ba3a22 100644 --- a/src/machine/machine_stm32l0x2.go +++ b/src/machine/machine_stm32l0x2.go @@ -245,8 +245,8 @@ func (t *TIM) enableMainOutput() { // nothing to do - no BDTR register } -type arrtype = uint16 -type arrRegType = volatile.Register16 +type arrtype = uint32 +type arrRegType = volatile.Register32 const ( ARR_MAX = 0x10000