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esp32: add interrupt-based UART RX and fix init order
Signed-off-by: deadprogram <ron@hybridgroup.com>
This commit is contained in:
deadprogram
@@ -412,19 +412,65 @@ var (
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TXRXSignal: 198,
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RTSCTSSignal: 199,
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}
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onceUart = sync.Once{}
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)
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// CPU interrupt line used for all UART peripherals.
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//
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// On the ESP32 (Xtensa LX6) the 32 CPU interrupt lines have fixed hardware
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// roles. Lines 6, 7, 11, 14, 15, 16 and 29 are internal (Xtensa timers,
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// software and profiling/NMI) and are NOT wired to the peripheral interrupt
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// matrix, so a peripheral routed to one of them via DPORT never fires.
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// The usable level-1 peripheral lines are 2, 3, 5, 8, 9, 10 (edge), 12, 13,
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// 17 and 18. We use line 8 for UART (9 is the timer alarm, 10 is GPIO).
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const cpuInterruptFromUART = 8
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// uartInterrupts is the set of UART interrupt flags we care about for RX.
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const uartInterrupts = esp.UART_INT_ENA_RXFIFO_FULL_INT_ENA |
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esp.UART_INT_ENA_RXFIFO_TOUT_INT_ENA |
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esp.UART_INT_ENA_PARITY_ERR_INT_ENA |
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esp.UART_INT_ENA_FRM_ERR_INT_ENA |
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esp.UART_INT_ENA_RXFIFO_OVF_INT_ENA |
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esp.UART_INT_ENA_GLITCH_DET_INT_ENA
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type UART struct {
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Bus *esp.UART_Type
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Buffer *RingBuffer
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TXRXSignal uint32
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RTSCTSSignal uint32
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Bus *esp.UART_Type
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Buffer *RingBuffer
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TXRXSignal uint32
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RTSCTSSignal uint32
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ParityErrorDetected bool
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DataErrorDetected bool
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DataOverflowDetected bool
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}
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func (uart *UART) Configure(config UARTConfig) {
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if config.BaudRate == 0 {
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config.BaudRate = 115200
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}
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// If no pins are specified (the zero value is GPIO0, which is never a
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// sensible default for both TX and RX), pick sensible defaults per UART.
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//
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// For UART0 (the console) we deliberately leave the pins untouched: the
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// ROM bootloader has already wired GPIO1 (TX) and GPIO3 (RX) directly via
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// the IO MUX to the USB-serial bridge. Re-routing them through the GPIO
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// matrix is unnecessary and can break RX, so we keep the bootloader setup
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// which is exactly what makes the boot log and greeting appear.
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if config.TX == 0 && config.RX == 0 {
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switch uart.Bus {
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case esp.UART0:
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config.TX = NoPin
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config.RX = NoPin
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case esp.UART1:
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config.TX = 10
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config.RX = 9
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case esp.UART2:
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config.TX = 17
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config.RX = 16
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}
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}
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uart.Bus.CLKDIV.Set(peripheralClock / config.BaudRate)
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if config.RX != NoPin {
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@@ -452,6 +498,101 @@ func (uart *UART) Configure(config UARTConfig) {
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if config.CTS != NoPin {
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config.CTS.configure(PinConfig{Mode: PinInputPullup}, uart.RTSCTSSignal)
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}
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uart.configureInterrupt()
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uart.enableReceiver()
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}
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func (uart *UART) configureInterrupt() {
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// Disable all UART interrupts while configuring.
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uart.Bus.INT_ENA.ClearBits(0x0ffff)
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// Map this UART's peripheral interrupt to a CPU interrupt line via DPORT.
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switch uart.Bus {
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case esp.UART0:
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esp.DPORT.SetPRO_UART_INTR_MAP(cpuInterruptFromUART)
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case esp.UART1:
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esp.DPORT.SetPRO_UART1_INTR_MAP(cpuInterruptFromUART)
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case esp.UART2:
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esp.DPORT.SetPRO_UART2_INTR_MAP(cpuInterruptFromUART)
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}
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// Register the ISR only once (shared across all UARTs on the same CPU int).
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// interrupt.New is a compiler intrinsic and requires a plain (non-capturing)
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// handler function, so we use a named package-level function.
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onceUart.Do(func() {
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_ = interrupt.New(cpuInterruptFromUART, handleUARTInterrupt).Enable()
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})
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}
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// handleUARTInterrupt is the shared UART interrupt handler. It must be a plain
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// function (not a closure) because interrupt.New is a compiler intrinsic that
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// does not support closures.
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func handleUARTInterrupt(interrupt.Interrupt) {
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UART0.serveInterrupt()
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UART1.serveInterrupt()
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UART2.serveInterrupt()
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}
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func (uart *UART) serveInterrupt() {
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// Check masked interrupt status.
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interruptFlag := uart.Bus.INT_ST.Get()
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if (interruptFlag & uartInterrupts) == 0 {
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return
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}
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// Block UART interrupts while processing.
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uart.Bus.INT_ENA.ClearBits(uartInterrupts)
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if interruptFlag&(esp.UART_INT_ENA_RXFIFO_FULL_INT_ENA|esp.UART_INT_ENA_RXFIFO_TOUT_INT_ENA) != 0 {
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for uart.Bus.GetSTATUS_RXFIFO_CNT() > 0 {
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// The ESP32 UART FIFO must be accessed through the AHB address
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// (base + 0x200C0000 == 0x60000000 for UART0), not the APB FIFO
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// register, due to a silicon erratum. This mirrors writeByte.
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b := (*volatile.Register8)(unsafe.Add(unsafe.Pointer(uart.Bus), 0x200C0000)).Get()
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if !uart.Buffer.Put(b) {
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uart.DataOverflowDetected = true
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}
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}
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}
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if interruptFlag&esp.UART_INT_ENA_PARITY_ERR_INT_ENA > 0 {
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uart.ParityErrorDetected = true
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}
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if interruptFlag&esp.UART_INT_ENA_FRM_ERR_INT_ENA != 0 {
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uart.DataErrorDetected = true
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}
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if interruptFlag&esp.UART_INT_ENA_RXFIFO_OVF_INT_ENA != 0 {
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uart.DataOverflowDetected = true
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}
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if interruptFlag&esp.UART_INT_ENA_GLITCH_DET_INT_ENA != 0 {
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uart.DataErrorDetected = true
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}
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// Clear the interrupt status bits.
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uart.Bus.INT_CLR.SetBits(interruptFlag)
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uart.Bus.INT_CLR.ClearBits(interruptFlag)
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// Re-enable UART interrupts.
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uart.Bus.INT_ENA.Set(uartInterrupts)
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}
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func (uart *UART) enableReceiver() {
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// Reset the RX FIFO.
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uart.Bus.SetCONF0_RXFIFO_RST(1)
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uart.Bus.SetCONF0_RXFIFO_RST(0)
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// Trigger interrupt when 1 byte is available (low latency).
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uart.Bus.SetCONF1_RXFIFO_FULL_THRHD(1)
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// Enable the RX timeout so that a single byte still generates an interrupt
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// once the line has been idle for the given number of bit periods. Without
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// this, RXFIFO_FULL only fires once more than the threshold has arrived.
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uart.Bus.SetCONF1_RX_TOUT_THRHD(2)
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uart.Bus.SetCONF1_RX_TOUT_EN(1)
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// Enable RX-related interrupts.
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uart.Bus.SetINT_ENA_RXFIFO_FULL_INT_ENA(1)
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uart.Bus.SetINT_ENA_RXFIFO_TOUT_INT_ENA(1)
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uart.Bus.SetINT_ENA_FRM_ERR_INT_ENA(1)
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uart.Bus.SetINT_ENA_PARITY_ERR_INT_ENA(1)
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uart.Bus.SetINT_ENA_GLITCH_DET_INT_ENA(1)
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uart.Bus.SetINT_ENA_RXFIFO_OVF_INT_ENA(1)
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}
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func (uart *UART) writeByte(b byte) error {
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@@ -47,18 +47,21 @@ func main() {
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// faster.
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clearbss()
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// Initialize UART.
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machine.InitSerial()
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// Initialize main system timer used for time.Now.
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initTimer()
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// Set up the Xtensa interrupt vector table.
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// Set up the Xtensa interrupt vector table. This zeroes INTENABLE, so it
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// must run before any peripheral (UART, timer, etc) enables its own CPU
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// interrupt line - otherwise that enable would be wiped out here.
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interruptInit()
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// Initialize timer alarm interrupt for the scheduler.
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initTimerInterrupt()
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// Initialize UART. This enables the UART RX interrupt, which must happen
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// after interruptInit so the INTENABLE bit is not cleared again.
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machine.InitSerial()
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// Initialize the heap, call main.main, etc.
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run()
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