From 7d6d93f7aa5554db353385d9a3c2b3710cddb14f Mon Sep 17 00:00:00 2001
From: Elias Naur <mail@eliasnaur.com>
Date: Tue, 4 Mar 2025 12:57:59 +0100
Subject: [PATCH] machine: bump rp2040 to 200MHz (#4768)

* machine: add support for core voltage adjustments to rp2040

In preparation for bumping the core frequency of the rp2040, this
change implements the required core voltage adjustment logic.

* machine: bump rp2040 to 200MHz
---
 src/machine/machine_rp2_2040.go   | 15 ++++++++++++++-
 src/machine/machine_rp2_2350.go   |  4 ++++
 src/machine/machine_rp2_clocks.go | 12 ++++++++++++
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/src/machine/machine_rp2_2040.go b/src/machine/machine_rp2_2040.go
index e7ae38c06..9cdb3a072 100644
--- a/src/machine/machine_rp2_2040.go
+++ b/src/machine/machine_rp2_2040.go
@@ -9,7 +9,7 @@ import (
 )
 
 const (
-	cpuFreq          = 125 * MHz
+	cpuFreq          = 200 * MHz
 	_NUMBANK0_GPIOS  = 30
 	_NUMBANK0_IRQS   = 4
 	_NUMIRQ          = 32
@@ -208,3 +208,16 @@ func (clks *clocksType) initTicks() {} // No ticks on RP2040
 func (wd *watchdogImpl) startTick(cycles uint32) {
 	rp.WATCHDOG.TICK.Set(cycles | rp.WATCHDOG_TICK_ENABLE)
 }
+
+func adjustCoreVoltage() bool {
+	if cpuFreq <= 133*MHz {
+		return false
+	}
+	// The rp2040 is certified to run at 200MHz with the
+	// core voltage set to 1150mV.
+	const targetVoltage = 1150
+	// 0b0101 maps to 800mV and each step is 50mV.
+	const vreg = 0b0101 + (targetVoltage-800)/50
+	rp.VREG_AND_CHIP_RESET.SetVREG_VSEL(vreg)
+	return true
+}
diff --git a/src/machine/machine_rp2_2350.go b/src/machine/machine_rp2_2350.go
index d20bb2d78..d259e750d 100644
--- a/src/machine/machine_rp2_2350.go
+++ b/src/machine/machine_rp2_2350.go
@@ -222,3 +222,7 @@ func EnterBootloader() {
 func (wd *watchdogImpl) startTick(cycles uint32) {
 	rp.TICKS.WATCHDOG_CTRL.SetBits(1)
 }
+
+func adjustCoreVoltage() bool {
+	return false
+}
diff --git a/src/machine/machine_rp2_clocks.go b/src/machine/machine_rp2_clocks.go
index 061f3dfe4..dafebbe5d 100644
--- a/src/machine/machine_rp2_clocks.go
+++ b/src/machine/machine_rp2_clocks.go
@@ -42,6 +42,10 @@ type clock struct {
 	cix clockIndex
 }
 
+// The delay in seconds for core voltage adjustments to
+// settle. Taken from the Pico SDK.
+const _VREG_VOLTAGE_AUTO_ADJUST_DELAY = 1 / 1e3
+
 // clock returns the clock identified by cix.
 func (clks *clocksType) clock(cix clockIndex) clock {
 	return clock{
@@ -188,6 +192,14 @@ func (clks *clocksType) init() {
 		xoscFreq,
 		xoscFreq)
 
+	if adjustCoreVoltage() {
+		// Wait for the voltage to settle.
+		const cycles = _VREG_VOLTAGE_AUTO_ADJUST_DELAY * xoscFreq * MHz
+		for i := 0; i < cycles; i++ {
+			arm.Asm("nop")
+		}
+	}
+
 	// clkSys = pllSys (125MHz) / 1 = 125MHz
 	csys := clks.clock(clkSys)
 	csys.configure(rp.CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX,