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Support for STM32L0 MCUs and Dragino LGT92 device (#1561)
machine/stm32l0: add support for stm32l0 family and Dragino LGT92 Board
This commit is contained in:
Fauchon
GitHub
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// +build stm32,stm32l0
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package runtime
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import (
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"device/arm"
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"device/stm32"
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"machine"
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"runtime/interrupt"
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"runtime/volatile"
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)
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const (
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// Sets PCLK1
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RCC_CFGR_PPRE1_DIV_NONE = 0x00000000
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RCC_CFGR_PPRE1_DIV_2 = 0x00000400
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RCC_CFGR_PPRE1_DIV_4 = 0x00000500
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RCC_CFGR_PPRE1_DIV_8 = 0x00000600
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RCC_CFGR_PPRE1_DIV_16 = 0x00000700
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// Sets PCLK2
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RCC_CFGR_PPRE2_DIV_NONE = 0x00000000
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RCC_CFGR_PPRE2_DIV_2 = 0x00002000
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RCC_CFGR_PPRE2_DIV_4 = 0x00002800
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RCC_CFGR_PPRE2_DIV_8 = 0x00003000
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RCC_CFGR_PPRE2_DIV_16 = 0x00003800
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)
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func init() {
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initCLK()
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initRTC()
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initTIM()
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machine.UART0.Configure(machine.UARTConfig{})
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}
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func putchar(c byte) {
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machine.UART0.WriteByte(c)
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}
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// initCLK sets clock to 32MHz
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// SEE: https://github.com/WRansohoff/STM32x0_timer_example/blob/master/src/main.c
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func initCLK() {
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// Set the Flash ACR to use 1 wait-state
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// enable the prefetch buffer and pre-read for performance
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stm32.Flash.ACR.SetBits(stm32.Flash_ACR_LATENCY | stm32.Flash_ACR_PRFTEN | stm32.Flash_ACR_PRE_READ)
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// Set presaclers so half system clock (PCLKx = HCLK/2)
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stm32.RCC.CFGR.SetBits(RCC_CFGR_PPRE1_DIV_2)
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stm32.RCC.CFGR.SetBits(RCC_CFGR_PPRE2_DIV_2)
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// Enable the HSI16 oscillator, since the L0 series boots to the MSI one.
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stm32.RCC.CR.SetBits(stm32.RCC_CR_HSI16ON)
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// Wait for HSI16 to be ready
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for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSI16RDYF) {
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}
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// Configure the PLL to use HSI16 with a PLLDIV of 2 and PLLMUL of 4.
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stm32.RCC.CFGR.SetBits(0x01<<stm32.RCC_CFGR_PLLDIV_Pos | 0x01<<stm32.RCC_CFGR_PLLMUL_Pos)
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stm32.RCC.CFGR.ClearBits(0x02<<stm32.RCC_CFGR_PLLDIV_Pos | 0x0E<<stm32.RCC_CFGR_PLLMUL_Pos)
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stm32.RCC.CFGR.ClearBits(stm32.RCC_CFGR_PLLSRC)
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// Enable PLL
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stm32.RCC.CR.SetBits(stm32.RCC_CR_PLLON)
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// Wait for PLL to be ready
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for !stm32.RCC.CR.HasBits(stm32.RCC_CR_PLLRDY) {
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}
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// Use PLL As System clock
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stm32.RCC.CFGR.SetBits(0x3)
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}
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var (
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timestamp timeUnit // microseconds since boottime
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timerLastCounter uint64
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)
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var timerWakeup volatile.Register8
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func initRTC() {
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// Enable power
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN)
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// access to backup register
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stm32.PWR.CR.SetBits(stm32.PWR_CR_DBP)
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// Enable LSE
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stm32.RCC.CSR.SetBits(stm32.RCC_CSR_LSEON)
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// wait until LSE is ready
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for !stm32.RCC.CSR.HasBits(stm32.RCC_CSR_LSERDY) {
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}
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// Select Clock Source LSE
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stm32.RCC.CSR.SetBits(0x01 << stm32.RCC_CSR_RTCSEL_Pos)
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stm32.RCC.CSR.ClearBits(0x02 << stm32.RCC_CSR_RTCSEL_Pos)
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// Enable clock
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stm32.RCC.CSR.SetBits(stm32.RCC_CSR_RTCEN)
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stm32.RTC.WPR.Set(0xCA) // Enable Write Access for RTC Registers
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stm32.RTC.WPR.Set(0x53) // Enable Write Access for RTC Registers
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stm32.RTC.ISR.SetBits(stm32.RTC_ISR_INIT) // Enable init phase
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// Wait for initialization state
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for !stm32.RTC.ISR.HasBits(stm32.RTC_ISR_INITF) {
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}
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stm32.RTC.PRER.Set(0x003F0270) // set prescaler, 40kHz/64 => 625Hz, 625Hz/625 => 1Hz
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// Set initial date
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//RTC->TR = RTC_TR_PM | 0;
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stm32.RTC.ISR.ClearBits(stm32.RTC_ISR_INIT) // Disable init phase
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stm32.RTC.WPR.Set(0xFE) // Disable Write Access for RTC Registers
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stm32.RTC.WPR.Set(0x64) // Disable Write Access for RTC Registers
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}
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// Enable the TIM3 clock.
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func initTIM() {
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM3EN)
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intr := interrupt.New(stm32.IRQ_TIM3, handleTIM3)
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intr.SetPriority(0xc3)
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intr.Enable()
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}
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const asyncScheduler = false
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func ticksToNanoseconds(ticks timeUnit) int64 {
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return int64(ticks) * 1000
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}
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func nanosecondsToTicks(ns int64) timeUnit {
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return timeUnit(ns / 1000)
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}
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// sleepTicks should sleep for specific number of microseconds.
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func sleepTicks(d timeUnit) {
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for d != 0 {
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ticks() // update timestamp
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ticks := uint32(d) // current scaling only supports 100 usec to 6553 msec
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timerSleep(ticks)
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d -= timeUnit(ticks)
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}
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}
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// number of ticks (microseconds) since start.
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func ticks() timeUnit {
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// Read twice to force shadow register cache update
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rSubSec := stm32.RTC.SSR.Get() & stm32.RTC_SSR_SS_Msk
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rSubSec = stm32.RTC.SSR.Get() & stm32.RTC_SSR_SS_Msk
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rDate := stm32.RTC.DR.Get()
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rDate = stm32.RTC.DR.Get()
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rDate++
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rTime := stm32.RTC.TR.Get()
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rTime = stm32.RTC.TR.Get()
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prediv := stm32.RTC.PRER.Get() & stm32.RTC_PRER_PREDIV_S_Msk
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var tsec uint64
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// Timestamp in seconds
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tsec = uint64(((rTime & 0x300000) >> 20) * 36000) // Hours Tens
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tsec += uint64(((rTime & 0xf0000) >> 16) * 3600) // Hours Units
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tsec += uint64(((rTime & 0x7000) >> 12) * 600) // Minutes Tens
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tsec += uint64(((rTime & 0xf00) >> 8) * 60) // Minutes Units
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tsec += uint64(((rTime & 0x70) >> 4) * 10) // Second Tens
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tsec += uint64(rTime & 0xf) // Seconds Units
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//Second fraction in milliseconds
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ssec := uint64((1000 * (prediv - rSubSec)) / (prediv + 1))
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timerCounter := uint64(tsec * 1000) // Timestamp in millis
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timerCounter += ssec // Add sub-seconds
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timerCounter *= 1000 // Convert to micros
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// change since last measurement
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offset := (timerCounter - timerLastCounter)
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timerLastCounter = timerCounter
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timestamp += timeUnit(offset)
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return timestamp
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}
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// ticks are in microseconds
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func timerSleep(ticks uint32) {
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timerWakeup.Set(0)
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// prescale counter down from 32mhz to 10khz aka 0.1 ms frequency.
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clk := machine.CPUFrequency() / 2
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stm32.TIM3.PSC.Set(clk/10000 - 1)
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// Set duty aka duration.
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// STM32 dividers use n-1, i.e. n counts from 0 to n-1.
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// As a result, with these prescaler settings,
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// the minimum allowed duration is 200 microseconds.
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if ticks < 200 {
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ticks = 200
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}
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stm32.TIM3.ARR.Set(ticks/100 - 1) // convert from microseconds to 0.1 ms
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// Enable the hardware interrupt.
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stm32.TIM3.DIER.SetBits(stm32.TIM_DIER_UIE)
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// Enable the timer.
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stm32.TIM3.CR1.SetBits(stm32.TIM_CR1_CEN)
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// wait till timer wakes up
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for timerWakeup.Get() == 0 {
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arm.Asm("wfi")
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}
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}
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func handleTIM3(interrupt.Interrupt) {
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if stm32.TIM3.SR.HasBits(stm32.TIM_SR_UIF) {
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// Disable the timer.
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stm32.TIM3.CR1.ClearBits(stm32.TIM_CR1_CEN)
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// clear the update flag
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stm32.TIM3.SR.ClearBits(stm32.TIM_SR_UIF)
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// timer was triggered
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timerWakeup.Set(1)
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}
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}
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