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machine,targets: add minimal esp32c6 implementation
This adds a minimal esp32c6 implementation, currently only supporting the examples/serial and examples/blinky1 programs. It does correctly output the expected "Hello, World" via the serial port, as well as blink the onboard LED. In addition, it adds support for the PLIC based IRQ handling as used on the ESP32C6 processor. Some parts of this code are loosely based on PR #5252 and #5248 Signed-off-by: deadprogram <ron@hybridgroup.com>
This commit is contained in:
deadprogram
@@ -0,0 +1,250 @@
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//go:build esp32c6
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package interrupt
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import (
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"device/riscv"
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"errors"
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"runtime/volatile"
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"unsafe"
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)
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//go:extern tinygo_saved_ra
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var tinygo_saved_ra uintptr
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// plicType maps the ESP32-C6 PLIC (Platform-Level Interrupt Controller)
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// machine-mode registers. The C6 uses the PLIC — not the INTPRI/INTC block
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// that the ESP32-C3 uses — as its CPU interrupt controller
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// (SOC_INT_PLIC_SUPPORTED). The INTPRI registers at 0x600c5000 are vestigial
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// backward-compatibility aliases on the C6 and are not wired to the CPU, so
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// writing them never delivers an interrupt.
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type plicType struct {
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MXINT_ENABLE volatile.Register32 // 0x00 bit N enables CPU interrupt line N
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MXINT_TYPE volatile.Register32 // 0x04 bit N: 1=edge, 0=level
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MXINT_CLEAR volatile.Register32 // 0x08 edge acknowledge
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MXINT_EIP_STATUS volatile.Register32 // 0x0C pending status (read-only)
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MXINT_PRI [32]volatile.Register32 // 0x10..0x8C per-line priority (4 bits)
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MXINT_THRESH volatile.Register32 // 0x90 priority threshold (8 bits)
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}
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// plic points at the PLIC machine-mode register block (DR_REG_PLIC_MX_BASE).
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var plic = (*plicType)(unsafe.Pointer(uintptr(0x20001000)))
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// Enable registers a CPU interrupt.
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// The ESP32-C6 has 31 CPU independent interrupts (1..31).
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func (i Interrupt) Enable() error {
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if i.num < 1 || i.num > 31 {
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return errors.New("interrupt for ESP32-C6 must be in range of 1 through 31")
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}
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mask := riscv.DisableInterrupts()
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defer riscv.EnableInterrupts(mask)
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// Enable CPU interrupt number i.num via the PLIC.
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plic.MXINT_ENABLE.SetBits(1 << i.num)
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// Set pulse interrupt type (rising edge detection).
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plic.MXINT_TYPE.SetBits(1 << i.num)
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// Set default priority (must be >= threshold to be delivered).
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plic.MXINT_PRI[i.num].Set(defaultThreshold)
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// Reset interrupt before re-enabling.
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plic.MXINT_CLEAR.SetBits(1 << i.num)
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plic.MXINT_CLEAR.ClearBits(1 << i.num)
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riscv.Asm("fence")
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return nil
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}
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// Adding pseudo function calls that is replaced by the compiler with the actual
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// functions registered through interrupt.New.
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//
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//go:linkname callHandlers runtime/interrupt.callHandlers
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func callHandlers(num int)
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//go:linkname signalInterrupt runtime.signalInterrupt
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func signalInterrupt()
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const (
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IRQNUM_1 = 1 + iota
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IRQNUM_2
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IRQNUM_3
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IRQNUM_4
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IRQNUM_5
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IRQNUM_6
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IRQNUM_7
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IRQNUM_8
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IRQNUM_9
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IRQNUM_10
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IRQNUM_11
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IRQNUM_12
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IRQNUM_13
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IRQNUM_14
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IRQNUM_15
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IRQNUM_16
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IRQNUM_17
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IRQNUM_18
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IRQNUM_19
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IRQNUM_20
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IRQNUM_21
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IRQNUM_22
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IRQNUM_23
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IRQNUM_24
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IRQNUM_25
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IRQNUM_26
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IRQNUM_27
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IRQNUM_28
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IRQNUM_29
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IRQNUM_30
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IRQNUM_31
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)
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const (
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defaultThreshold = 5
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// Priority 0 disables an interrupt on ESP32-C6.
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disableThreshold = 0
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)
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//go:inline
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func callHandler(n int) {
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switch n {
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case IRQNUM_1:
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callHandlers(IRQNUM_1)
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case IRQNUM_2:
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callHandlers(IRQNUM_2)
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case IRQNUM_3:
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callHandlers(IRQNUM_3)
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case IRQNUM_4:
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callHandlers(IRQNUM_4)
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case IRQNUM_5:
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callHandlers(IRQNUM_5)
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case IRQNUM_6:
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callHandlers(IRQNUM_6)
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case IRQNUM_7:
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callHandlers(IRQNUM_7)
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case IRQNUM_8:
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callHandlers(IRQNUM_8)
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case IRQNUM_9:
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callHandlers(IRQNUM_9)
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case IRQNUM_10:
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callHandlers(IRQNUM_10)
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case IRQNUM_11:
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callHandlers(IRQNUM_11)
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case IRQNUM_12:
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callHandlers(IRQNUM_12)
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case IRQNUM_13:
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callHandlers(IRQNUM_13)
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case IRQNUM_14:
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callHandlers(IRQNUM_14)
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case IRQNUM_15:
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callHandlers(IRQNUM_15)
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case IRQNUM_16:
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callHandlers(IRQNUM_16)
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case IRQNUM_17:
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callHandlers(IRQNUM_17)
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case IRQNUM_18:
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callHandlers(IRQNUM_18)
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case IRQNUM_19:
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callHandlers(IRQNUM_19)
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case IRQNUM_20:
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callHandlers(IRQNUM_20)
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case IRQNUM_21:
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callHandlers(IRQNUM_21)
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case IRQNUM_22:
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callHandlers(IRQNUM_22)
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case IRQNUM_23:
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callHandlers(IRQNUM_23)
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case IRQNUM_24:
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callHandlers(IRQNUM_24)
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case IRQNUM_25:
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callHandlers(IRQNUM_25)
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case IRQNUM_26:
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callHandlers(IRQNUM_26)
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case IRQNUM_27:
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callHandlers(IRQNUM_27)
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case IRQNUM_28:
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callHandlers(IRQNUM_28)
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case IRQNUM_29:
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callHandlers(IRQNUM_29)
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case IRQNUM_30:
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callHandlers(IRQNUM_30)
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case IRQNUM_31:
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callHandlers(IRQNUM_31)
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}
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}
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//export handleInterrupt
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func handleInterrupt() {
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mcause := riscv.MCAUSE.Get()
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exception := mcause&(1<<31) == 0
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interruptNumber := uint32(mcause & 0x1f)
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if !exception && interruptNumber > 0 {
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// Save MSTATUS & MEPC, which could be overwritten by another CPU interrupt.
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mstatus := riscv.MSTATUS.Get()
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mepc := riscv.MEPC.Get()
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// Temporarily disable this interrupt by lowering its PLIC priority
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// below the threshold.
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thresholdSave := plic.MXINT_PRI[interruptNumber].Get()
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plic.MXINT_PRI[interruptNumber].Set(disableThreshold)
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riscv.Asm("fence")
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interruptBit := uint32(1 << interruptNumber)
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// Reset pending status interrupt.
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if plic.MXINT_TYPE.Get()&interruptBit != 0 {
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// Edge type interrupt.
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plic.MXINT_CLEAR.SetBits(interruptBit)
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plic.MXINT_CLEAR.ClearBits(interruptBit)
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} else {
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// Level type interrupt.
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plic.MXINT_CLEAR.ClearBits(interruptBit)
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}
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// Enable CPU interrupts.
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riscv.MSTATUS.SetBits(riscv.MSTATUS_MIE)
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// Call registered interrupt handler(s).
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callHandler(int(interruptNumber))
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// Signal to sleepTicks that an interrupt has occurred.
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signalInterrupt()
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// Disable CPU interrupts.
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riscv.MSTATUS.ClearBits(riscv.MSTATUS_MIE)
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// Restore interrupt priority to enable interrupt again.
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plic.MXINT_PRI[interruptNumber].Set(thresholdSave)
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riscv.Asm("fence")
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// Zero MCAUSE so that interrupt.In() returns false once we
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// return to normal (non-interrupt) code.
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riscv.MCAUSE.Set(0)
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// Restore MSTATUS & MEPC.
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riscv.MSTATUS.Set(mstatus)
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riscv.MEPC.Set(mepc)
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} else {
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handleException(mcause)
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}
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}
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func handleException(mcause uintptr) {
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println("*** Exception: pc:", riscv.MEPC.Get())
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println("*** Exception: code:", uint32(mcause&0x1f))
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println("*** Exception: mcause:", mcause)
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println("*** Exception: ra:", tinygo_saved_ra)
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switch uint32(mcause & 0x1f) {
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case riscv.InstructionAccessFault:
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println("*** virtual address:", riscv.MTVAL.Get())
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case riscv.IllegalInstruction:
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println("*** opcode:", riscv.MTVAL.Get())
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case riscv.LoadAccessFault:
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println("*** read address:", riscv.MTVAL.Get())
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case riscv.StoreOrAMOAccessFault:
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println("*** write address:", riscv.MTVAL.Get())
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}
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for {
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riscv.Asm("wfi")
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}
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}
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@@ -0,0 +1,211 @@
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//go:build esp32c6
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package runtime
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import (
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"device/esp"
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"device/riscv"
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"machine"
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"runtime/interrupt"
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"runtime/volatile"
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"unsafe"
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)
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// This is the function called on startup after the flash (IROM/DROM) is
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// initialized and the stack pointer has been set.
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//
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//export main
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func main() {
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// This initialization configures the following things:
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// * It disables all watchdog timers. They might be useful at some point in
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// the future, but will need integration into the scheduler. For now,
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// they're all disabled.
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// * It sets the CPU frequency to 160MHz, which is the maximum speed allowed
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// for this CPU. Lower frequencies might be possible in the future, but
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// running fast and sleeping quickly is often also a good strategy to save
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// power.
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// Disable Timer Group 0 watchdog (unlock first).
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esp.TIMG0.WDTWPROTECT.Set(0x50D83AA1)
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esp.TIMG0.WDTCONFIG0.Set(0)
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// Disable Timer Group 1 watchdog (unlock first).
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esp.TIMG1.WDTWPROTECT.Set(0x50D83AA1)
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esp.TIMG1.WDTCONFIG0.Set(0)
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// Disable LP watchdog (write-protect key first).
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esp.LP_WDT.WDTWPROTECT.Set(0x50D83AA1)
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esp.LP_WDT.WDTCONFIG0.Set(0)
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// Disable super watchdog.
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esp.LP_WDT.SWD_WPROTECT.Set(0x50D83AA1)
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esp.LP_WDT.SWD_CONF.SetBits(1 << 30) // SWD_DISABLE bit
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// Change CPU frequency to 160MHz from SPLL (480MHz).
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//
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// Clock tree: SPLL (480MHz) → HP root → CPU / AHB / APB
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//
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// Set dividers BEFORE switching the clock source so the first PLL
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// cycle already arrives divided:
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// HP root = SPLL / (HS_DIV_NUM+1) = 480 / 3 = 160 MHz
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// CPU = HP root / (CPU_HS_DIV_NUM+1) = 160 / 1 = 160 MHz
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// AHB = HP root / (AHB_HS_DIV_NUM+1) = 160 / 4 = 40 MHz
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// APB = AHB / (APB_HS_DIV_NUM+1) = 40 / 1 = 40 MHz
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esp.PCR.CPU_FREQ_CONF.Set(0 << 8) // CPU_HS_DIV_NUM = 0 (div1)
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esp.PCR.AHB_FREQ_CONF.Set(3 << 8) // AHB_HS_DIV_NUM = 3 (div4)
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esp.PCR.APB_FREQ_CONF.Set(0 << 8) // APB_HS_DIV_NUM = 0 (div1)
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// Switch to PLL: SOC_CLK_SEL = 1 (SPLL), HS_DIV_NUM = 2 (div3).
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esp.PCR.SYSCLK_CONF.Set(1<<16 | 2<<8)
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clearbss()
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// Configure interrupt handler
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interruptInit()
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// Initialize main system timer used for time.Now.
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initTimer()
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// Initialize timer alarm interrupt for the scheduler.
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initTimerInterrupt()
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// Initialize the heap, call main.main, etc.
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run()
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// Fallback: if main ever returns, hang the CPU.
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exit(0)
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}
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func init() {
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machine.InitSerial()
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}
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func abort() {
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for {
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riscv.Asm("wfi")
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}
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}
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// interruptInit initializes the interrupt controller.
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func interruptInit() {
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mie := riscv.DisableInterrupts()
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// Reset all interrupt priorities to zero in the PLIC.
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for i := 1; i < 32; i++ {
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plic.MXINT_PRI[i].Set(0)
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}
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// Default threshold for interrupts is 5.
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plic.MXINT_THRESH.Set(5)
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// Set the interrupt address.
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// Set MODE field to 1 - a vector base address.
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// Note that this address must be aligned to 256 bytes.
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riscv.MTVEC.Set((uintptr(unsafe.Pointer(&_vector_table))) | 1)
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// On the ESP32-C6 the CPU receives PLIC interrupts through the standard
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// RISC-V mie CSR (machine interrupt-enable, 0x304). Unlike the ESP32-C3's
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// INTC, the PLIC's per-line interrupts are gated by mie, so it must be
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// enabled for any interrupt to reach the CPU. esp-hal does the same thing
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// for the PLIC: `csrw mie, 0xffffffff`.
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riscv.MIE.Set(0xffffffff)
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// Globally enable machine-mode interrupts (MSTATUS.MIE).
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//
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// Unlike the ESP32-C3, whose ROM bootloader hands control to the
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// application with MSTATUS.MIE already set, the ESP32-C6 ROM leaves it
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// cleared. Restoring the previous state (riscv.EnableInterrupts(mie))
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// would therefore leave interrupts globally disabled, so no interrupt is
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// ever delivered to the CPU: timer alarms silently fall back to the
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// polling loop in sleepTicks and peripheral RX interrupts (such as the
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// USB Serial/JTAG controller) never fire. Set the bit explicitly instead.
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_ = mie
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riscv.MSTATUS.SetBits(riscv.MSTATUS_MIE)
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}
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// CPU interrupt number used for the TIMG0 timer alarm.
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const timerAlarmCPUInterrupt = 9
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var interruptPending volatile.Register8
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func signalInterrupt() {
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interruptPending.Set(1)
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}
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// initTimerInterrupt routes the TIMG0 timer 0 alarm interrupt to a CPU
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// interrupt and registers a handler.
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func initTimerInterrupt() {
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// Map the TIMG0 T0 peripheral interrupt to a CPU interrupt line.
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// On C6, INTERRUPT_CORE0 is for peripheral→CPU interrupt mapping.
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esp.INTERRUPT_CORE0.TG0_T0_INTR_MAP.Set(timerAlarmCPUInterrupt)
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// Enable T0 interrupt at the timer group level.
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esp.TIMG0.INT_ENA_TIMERS.SetBits(1)
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// Register the interrupt handler.
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interrupt.New(timerAlarmCPUInterrupt, func(interrupt.Interrupt) {
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esp.TIMG0.INT_CLR_TIMERS.Set(1)
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})
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// Enable the CPU interrupt:
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mie := riscv.DisableInterrupts()
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// Clear any stale pending bit.
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plic.MXINT_CLEAR.SetBits(1 << timerAlarmCPUInterrupt)
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plic.MXINT_CLEAR.ClearBits(1 << timerAlarmCPUInterrupt)
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// Set edge-triggered.
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plic.MXINT_TYPE.SetBits(1 << timerAlarmCPUInterrupt)
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// Set priority above threshold.
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plic.MXINT_PRI[timerAlarmCPUInterrupt].Set(10)
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riscv.Asm("fence")
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plic.MXINT_ENABLE.SetBits(1 << timerAlarmCPUInterrupt)
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riscv.EnableInterrupts(mie)
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}
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// sleepTicks spins until the given number of ticks have elapsed, using the
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// TIMG0 alarm interrupt to avoid busy-waiting for the entire duration.
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func sleepTicks(d timeUnit) {
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machine.FlushSerial()
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target := ticks() + d
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for ticks() < target {
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interruptPending.Set(0)
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esp.TIMG0.T0ALARMLO.Set(uint32(target))
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esp.TIMG0.T0ALARMHI.Set(uint32(target >> 32))
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// Enable the alarm (auto-clears when alarm fires).
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esp.TIMG0.T0CONFIG.SetBits(esp.TIMG_T0CONFIG_ALARM_EN)
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for interruptPending.Get() == 0 {
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if ticks() >= target {
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return
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}
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}
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}
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}
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//go:extern _vector_table
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var _vector_table [0]uintptr
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// plicType maps the ESP32-C6 PLIC (Platform-Level Interrupt Controller)
|
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// machine-mode registers. The C6 uses the PLIC — not the INTPRI/INTC block
|
||||
// that the ESP32-C3 uses — as its CPU interrupt controller
|
||||
// (SOC_INT_PLIC_SUPPORTED). The INTPRI registers at 0x600c5000 are vestigial
|
||||
// backward-compatibility aliases on the C6 and are not wired to the CPU, so
|
||||
// writing them never delivers an interrupt.
|
||||
type plicType struct {
|
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MXINT_ENABLE volatile.Register32 // 0x00 bit N enables CPU interrupt line N
|
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MXINT_TYPE volatile.Register32 // 0x04 bit N: 1=edge, 0=level
|
||||
MXINT_CLEAR volatile.Register32 // 0x08 edge acknowledge
|
||||
MXINT_EIP_STATUS volatile.Register32 // 0x0C pending status (read-only)
|
||||
MXINT_PRI [32]volatile.Register32 // 0x10..0x8C per-line priority (4 bits)
|
||||
MXINT_THRESH volatile.Register32 // 0x90 priority threshold (8 bits)
|
||||
}
|
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|
||||
// plic points at the PLIC machine-mode register block (DR_REG_PLIC_MX_BASE).
|
||||
var plic = (*plicType)(unsafe.Pointer(uintptr(0x20001000)))
|
||||
@@ -1,4 +1,4 @@
|
||||
//go:build esp32 || esp32c3
|
||||
//go:build esp32 || esp32c3 || esp32c6
|
||||
|
||||
package runtime
|
||||
|
||||
|
||||
Reference in New Issue
Block a user