mirror of
https://github.com/tinygo-org/tinygo.git
synced 2026-08-07 12:33:42 +00:00
Working on NXP/Teensy support
This commit is contained in:
Ethan Reesor
Ron Evans
@@ -6,12 +6,12 @@ import (
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"device/nxp"
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)
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//go:keep
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//go:section .flashconfig
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var FlashConfig = [16]byte{
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xDE, 0xF9, 0xFF, 0xFF,
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}
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// //go:keep
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// //go:section .flash_config
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// var FlashControl = [16]byte{
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// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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// 0xFF, 0xFF, 0xFF, 0xFF, 0xDE, 0xF9, 0xFF, 0xFF,
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// }
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func CPUFrequency() uint32 {
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return 180000000
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@@ -20,20 +20,73 @@ func CPUFrequency() uint32 {
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// LED on the Teensy
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const LED Pin = 13
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var _pinRegisters [64]pinRegisters
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func init() {
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_pinRegisters[13].Bit = 5
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_pinRegisters[13].PCR = &nxp.PORTC.PCR5
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_pinRegisters[13].PDOR = nxp.GPIOC.PDOR.Bit(5)
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_pinRegisters[13].PSOR = nxp.GPIOC.PSOR.Bit(5)
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_pinRegisters[13].PCOR = nxp.GPIOC.PCOR.Bit(5)
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_pinRegisters[13].PTOR = nxp.GPIOC.PTOR.Bit(5)
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_pinRegisters[13].PDIR = nxp.GPIOC.PDIR.Bit(5)
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_pinRegisters[13].PDDR = nxp.GPIOC.PDDR.Bit(5)
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var pins = []pin{
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// {bit, control register, gpio register bank}
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0: {16, &nxp.PORTB.PCR16, nxp.GPIOB},
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1: {17, &nxp.PORTB.PCR17, nxp.GPIOB},
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2: {0, &nxp.PORTD.PCR0, nxp.GPIOD},
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3: {12, &nxp.PORTA.PCR12, nxp.GPIOA},
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4: {13, &nxp.PORTA.PCR13, nxp.GPIOA},
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5: {7, &nxp.PORTD.PCR7, nxp.GPIOD},
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6: {4, &nxp.PORTD.PCR4, nxp.GPIOD},
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7: {2, &nxp.PORTD.PCR2, nxp.GPIOD},
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8: {3, &nxp.PORTD.PCR3, nxp.GPIOD},
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9: {3, &nxp.PORTC.PCR3, nxp.GPIOC},
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10: {4, &nxp.PORTC.PCR4, nxp.GPIOC},
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11: {6, &nxp.PORTC.PCR6, nxp.GPIOC},
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12: {7, &nxp.PORTC.PCR7, nxp.GPIOC},
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13: {5, &nxp.PORTC.PCR5, nxp.GPIOC},
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14: {1, &nxp.PORTD.PCR1, nxp.GPIOD},
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15: {0, &nxp.PORTC.PCR0, nxp.GPIOC},
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16: {0, &nxp.PORTB.PCR0, nxp.GPIOB},
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17: {1, &nxp.PORTB.PCR1, nxp.GPIOB},
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18: {3, &nxp.PORTB.PCR3, nxp.GPIOB},
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19: {2, &nxp.PORTB.PCR2, nxp.GPIOB},
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20: {5, &nxp.PORTD.PCR5, nxp.GPIOD},
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21: {6, &nxp.PORTD.PCR6, nxp.GPIOD},
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22: {1, &nxp.PORTC.PCR1, nxp.GPIOC},
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23: {2, &nxp.PORTC.PCR2, nxp.GPIOC},
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24: {26, &nxp.PORTE.PCR26, nxp.GPIOE},
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25: {5, &nxp.PORTA.PCR5, nxp.GPIOA},
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26: {14, &nxp.PORTA.PCR14, nxp.GPIOA},
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27: {15, &nxp.PORTA.PCR15, nxp.GPIOA},
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28: {16, &nxp.PORTA.PCR16, nxp.GPIOA},
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29: {18, &nxp.PORTB.PCR18, nxp.GPIOB},
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30: {19, &nxp.PORTB.PCR19, nxp.GPIOB},
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31: {10, &nxp.PORTB.PCR10, nxp.GPIOB},
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32: {11, &nxp.PORTB.PCR11, nxp.GPIOB},
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33: {24, &nxp.PORTE.PCR24, nxp.GPIOE},
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34: {25, &nxp.PORTE.PCR25, nxp.GPIOE},
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35: {8, &nxp.PORTC.PCR8, nxp.GPIOC},
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36: {9, &nxp.PORTC.PCR9, nxp.GPIOC},
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37: {10, &nxp.PORTC.PCR10, nxp.GPIOC},
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38: {11, &nxp.PORTC.PCR11, nxp.GPIOC},
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39: {17, &nxp.PORTA.PCR17, nxp.GPIOA},
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40: {28, &nxp.PORTA.PCR28, nxp.GPIOA},
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41: {29, &nxp.PORTA.PCR29, nxp.GPIOA},
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42: {26, &nxp.PORTA.PCR26, nxp.GPIOA},
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43: {20, &nxp.PORTB.PCR20, nxp.GPIOB},
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44: {22, &nxp.PORTB.PCR22, nxp.GPIOB},
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45: {23, &nxp.PORTB.PCR23, nxp.GPIOB},
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46: {21, &nxp.PORTB.PCR21, nxp.GPIOB},
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47: {8, &nxp.PORTD.PCR8, nxp.GPIOD},
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48: {9, &nxp.PORTD.PCR9, nxp.GPIOD},
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49: {4, &nxp.PORTB.PCR4, nxp.GPIOB},
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50: {5, &nxp.PORTB.PCR5, nxp.GPIOB},
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51: {14, &nxp.PORTD.PCR14, nxp.GPIOD},
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52: {13, &nxp.PORTD.PCR13, nxp.GPIOD},
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53: {12, &nxp.PORTD.PCR12, nxp.GPIOD},
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54: {15, &nxp.PORTD.PCR15, nxp.GPIOD},
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55: {11, &nxp.PORTD.PCR11, nxp.GPIOD},
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56: {10, &nxp.PORTE.PCR10, nxp.GPIOE},
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57: {11, &nxp.PORTE.PCR11, nxp.GPIOE},
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58: {0, &nxp.PORTE.PCR0, nxp.GPIOE},
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59: {1, &nxp.PORTE.PCR1, nxp.GPIOE},
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60: {2, &nxp.PORTE.PCR2, nxp.GPIOE},
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61: {3, &nxp.PORTE.PCR3, nxp.GPIOE},
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62: {4, &nxp.PORTE.PCR4, nxp.GPIOE},
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63: {5, &nxp.PORTE.PCR5, nxp.GPIOE},
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}
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//go:inline
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func (p Pin) registers() pinRegisters {
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return _pinRegisters[p]
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}
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func (p Pin) reg() pin { return pins[p] }
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@@ -44,3 +44,9 @@ func (rb *RingBuffer) Get() (byte, bool) {
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}
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return 0, false
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}
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// Clear resets the head and tail pointer to zero.
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func (rb *RingBuffer) Clear() {
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rb.head.Set(0)
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rb.tail.Set(0)
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}
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@@ -7,19 +7,7 @@ import (
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"runtime/volatile"
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)
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const (
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PortControlRegisterSRE = nxp.PORT_PCR0_SRE
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PortControlRegisterDSE = nxp.PORT_PCR0_DSE
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PortControlRegisterODE = nxp.PORT_PCR0_ODE
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)
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func PortControlRegisterMUX(v uint8) uint32 {
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return (uint32(v) << nxp.PORT_PCR0_MUX_Pos) & nxp.PORT_PCR0_MUX_Msk
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}
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type pinRegisters struct {
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Bit uintptr
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PCR *volatile.Register32
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type FastPin struct {
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PDOR *volatile.BitRegister
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PSOR *volatile.BitRegister
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PCOR *volatile.BitRegister
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@@ -28,6 +16,12 @@ type pinRegisters struct {
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PDDR *volatile.BitRegister
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}
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type pin struct {
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Bit uint8
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PCR *volatile.Register32
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GPIO *nxp.GPIO_Type
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}
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// Configure this pin with the given configuration.
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func (p Pin) Configure(config PinConfig) {
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switch config.Mode {
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@@ -35,22 +29,47 @@ func (p Pin) Configure(config PinConfig) {
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panic("todo")
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case PinOutput:
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p.registers().PDDR.Set()
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p.registers().PCR.SetBits(PortControlRegisterSRE | PortControlRegisterDSE | PortControlRegisterMUX(1))
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p.registers().PCR.ClearBits(PortControlRegisterODE)
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r := p.reg()
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r.GPIO.PDDR.SetBits(1 << r.Bit)
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r.PCR.SetBits(nxp.PORT_PCR0_SRE | nxp.PORT_PCR0_DSE | nxp.PORT_PCR0_MUX(1))
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r.PCR.ClearBits(nxp.PORT_PCR0_ODE)
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}
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}
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// Set changes the value of the GPIO pin. The pin must be configured as output.
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func (p Pin) Set(value bool) {
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r := p.reg()
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if value {
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p.registers().PSOR.Set()
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r.GPIO.PSOR.Set(1 << r.Bit)
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} else {
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p.registers().PCOR.Set()
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r.GPIO.PCOR.Set(1 << r.Bit)
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}
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}
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// Get returns the current value of a GPIO pin.
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func (p Pin) Get() bool {
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return p.registers().PDIR.Get()
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r := p.reg()
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return r.GPIO.PDIR.HasBits(1 << r.Bit)
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}
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func (p Pin) Control() *volatile.Register32 {
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return p.reg().PCR
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}
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func (p Pin) Fast() FastPin {
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r := p.reg()
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return FastPin{
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PDOR: r.GPIO.PDOR.Bit(r.Bit),
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PSOR: r.GPIO.PSOR.Bit(r.Bit),
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PCOR: r.GPIO.PCOR.Bit(r.Bit),
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PTOR: r.GPIO.PTOR.Bit(r.Bit),
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PDIR: r.GPIO.PDIR.Bit(r.Bit),
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PDDR: r.GPIO.PDDR.Bit(r.Bit),
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}
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}
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func (p FastPin) Set() { p.PSOR.Set(true) }
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func (p FastPin) Clear() { p.PCOR.Set(true) }
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func (p FastPin) Toggle() { p.PTOR.Set(true) }
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func (p FastPin) Write(v bool) { p.PDOR.Set(v) }
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func (p FastPin) Read() bool { return p.PDIR.Get() }
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@@ -0,0 +1,251 @@
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// +build nxp,mk66f18
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package machine
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import (
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"device/arm"
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"device/nxp"
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"errors"
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"runtime/volatile"
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_ "unsafe" // for go:linkname
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)
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const (
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uartC2Enable = nxp.UART_C2_TE | nxp.UART_C2_RE | nxp.UART_C2_RIE | nxp.UART_C2_ILIE
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uartC2TXActive = uartC2Enable | nxp.UART_C2_TIE
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uartC2TXCompleting = uartC2Enable | nxp.UART_C2_TCIE
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uartC2TXInactive = uartC2Enable
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uartIRQPriority = 64
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)
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var (
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ErrNotImplemented = errors.New("device has not been implemented")
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ErrNotConfigured = errors.New("device has not been configured")
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)
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type UARTConfig struct {
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BaudRate uint32
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}
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type UART struct {
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*nxp.UART_Type
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RXPCR *volatile.Register32
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TXPCR *volatile.Register32
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SCGC *volatile.Register32
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SCGCMask uint32
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IRQNumber uint32
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// state
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RXBuffer RingBuffer
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TXBuffer RingBuffer
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Transmitting volatile.Register8
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}
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// 'UART0' in the K66 manual corresponds to 'UART1' on the Teensy's pinout
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var UART1 = UART{UART_Type: nxp.UART0, RXPCR: pins[0].PCR, TXPCR: pins[1].PCR, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART0, IRQNumber: nxp.IRQ_UART0_RX_TX}
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var UART2 = UART{UART_Type: nxp.UART1, RXPCR: pins[9].PCR, TXPCR: pins[10].PCR, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART1, IRQNumber: nxp.IRQ_UART1_RX_TX}
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var UART3 = UART{UART_Type: nxp.UART2, RXPCR: pins[7].PCR, TXPCR: pins[8].PCR, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART2, IRQNumber: nxp.IRQ_UART2_RX_TX}
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var UART4 = UART{UART_Type: nxp.UART3, RXPCR: pins[31].PCR, TXPCR: pins[32].PCR, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART3, IRQNumber: nxp.IRQ_UART3_RX_TX}
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var UART5 = UART{UART_Type: nxp.UART4, RXPCR: pins[34].PCR, TXPCR: pins[33].PCR, SCGC: &nxp.SIM.SCGC1, SCGCMask: nxp.SIM_SCGC1_UART4, IRQNumber: nxp.IRQ_UART4_RX_TX}
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//go:export UART0_RX_TX_IRQHandler
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func uart0StatusISR() { UART1.handleStatusInterrupt() }
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//go:export UART1_RX_TX_IRQHandler
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func uart1StatusISR() { UART2.handleStatusInterrupt() }
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//go:export UART2_RX_TX_IRQHandler
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func uart2StatusISR() { UART3.handleStatusInterrupt() }
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//go:export UART3_RX_TX_IRQHandler
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func uart3StatusISR() { UART4.handleStatusInterrupt() }
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//go:export UART4_RX_TX_IRQHandler
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func uart4StatusISR() { UART5.handleStatusInterrupt() }
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// Configure the UART.
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func (u *UART) Configure(config UARTConfig) {
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en := u.SCGC.HasBits(u.SCGCMask)
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// adapted from Teensy core's serial_begin
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if !en {
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u.Transmitting.Set(0)
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// turn on the clock
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u.SCGC.Set(u.SCGCMask)
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// configure pins
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u.RXPCR.Set(nxp.PORT_PCR0_PE | nxp.PORT_PCR0_PS | nxp.PORT_PCR0_PFE | nxp.PORT_PCR0_MUX(3))
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u.TXPCR.Set(nxp.PORT_PCR0_DSE | nxp.PORT_PCR0_SRE | nxp.PORT_PCR0_MUX(3))
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u.C1.Set(nxp.UART_C1_ILT)
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}
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// default to 115200 baud
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if config.BaudRate == 0 {
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config.BaudRate = 115200
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}
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// copied from teensy core's BAUD2DIV macro
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divisor := ((CPUFrequency() * 2) + ((config.BaudRate) >> 1)) / config.BaudRate
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if divisor < 32 {
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divisor = 32
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}
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if en {
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// don't change baud rate mid transmit
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u.Flush()
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}
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// set the divisor
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u.BDH.Set(uint8((divisor >> 13) & 0x1F))
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u.BDL.Set(uint8((divisor >> 5) & 0xFF))
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u.C4.Set(uint8(divisor & 0x1F))
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if !en {
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u.C1.Set(nxp.UART_C1_ILT)
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// configure TX and RX watermark
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u.TWFIFO.Set(2) // causes bit TDRE of S1 to set
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u.RWFIFO.Set(4) // causes bit RDRF of S1 to set
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u.PFIFO.Set(nxp.UART_PFIFO_TXFE | nxp.UART_PFIFO_RXFE)
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u.C2.Set(uartC2TXInactive)
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arm.SetPriority(u.IRQNumber, uartIRQPriority)
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arm.EnableIRQ(u.IRQNumber)
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}
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}
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|
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func (u *UART) Disable() {
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// adapted from Teensy core's serial_end
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// check if the device has been enabled already
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if !u.SCGC.HasBits(u.SCGCMask) {
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return
|
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}
|
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|
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u.Flush()
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|
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arm.DisableIRQ(u.IRQNumber)
|
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u.C2.Set(0)
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// reconfigure pin
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u.RXPCR.Set(nxp.PORT_PCR0_PE | nxp.PORT_PCR0_PS | nxp.PORT_PCR0_MUX(1))
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u.TXPCR.Set(nxp.PORT_PCR0_PE | nxp.PORT_PCR0_PS | nxp.PORT_PCR0_MUX(1))
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// clear flags
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u.S1.Get()
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u.D.Get()
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u.RXBuffer.Clear()
|
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}
|
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|
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func (u *UART) Flush() {
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for u.Transmitting.Get() != 0 {
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// gosched()
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}
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}
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// adapted from Teensy core's uart0_status_isr
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func (u *UART) handleStatusInterrupt() {
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if u.S1.HasBits(nxp.UART_S1_RDRF | nxp.UART_S1_IDLE) {
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intrs := arm.DisableInterrupts()
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avail := u.RCFIFO.Get()
|
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if avail == 0 {
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// The only way to clear the IDLE interrupt flag is
|
||||
// to read the data register. But reading with no
|
||||
// data causes a FIFO underrun, which causes the
|
||||
// FIFO to return corrupted data. If anyone from
|
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// Freescale reads this, what a poor design! There
|
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// write should be a write-1-to-clear for IDLE.
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u.D.Get()
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// flushing the fifo recovers from the underrun,
|
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// but there's a possible race condition where a
|
||||
// new character could be received between reading
|
||||
// RCFIFO == 0 and flushing the FIFO. To minimize
|
||||
// the chance, interrupts are disabled so a higher
|
||||
// priority interrupt (hopefully) doesn't delay.
|
||||
// TODO: change this to disabling the IDLE interrupt
|
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// which won't be simple, since we already manage
|
||||
// which transmit interrupts are enabled.
|
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u.CFIFO.Set(nxp.UART_CFIFO_RXFLUSH)
|
||||
arm.EnableInterrupts(intrs)
|
||||
|
||||
} else {
|
||||
arm.EnableInterrupts(intrs)
|
||||
|
||||
for {
|
||||
u.RXBuffer.Put(u.D.Get())
|
||||
avail--
|
||||
if avail <= 0 {
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
c := u.C2.Get()
|
||||
if c&nxp.UART_C2_TIE != 0 && u.S1.HasBits(nxp.UART_S1_TDRE) {
|
||||
for {
|
||||
n, ok := u.TXBuffer.Get()
|
||||
if !ok {
|
||||
break
|
||||
}
|
||||
|
||||
u.S1.Get()
|
||||
u.D.Set(n)
|
||||
|
||||
if u.TCFIFO.Get() >= 8 {
|
||||
break
|
||||
}
|
||||
}
|
||||
|
||||
if u.S1.HasBits(nxp.UART_S1_TDRE) {
|
||||
u.Transmitting.Set(0)
|
||||
u.C2.Set(uartC2TXCompleting)
|
||||
}
|
||||
}
|
||||
|
||||
if c&nxp.UART_C2_TCIE != 0 && u.S1.HasBits(nxp.UART_S1_TC) {
|
||||
u.C2.Set(uartC2TXInactive)
|
||||
}
|
||||
}
|
||||
|
||||
//go:linkname gosched runtime.Gosched
|
||||
func gosched()
|
||||
|
||||
// WriteByte writes a byte of data to the UART.
|
||||
func (u *UART) WriteByte(c byte) error {
|
||||
if !u.SCGC.HasBits(u.SCGCMask) {
|
||||
return ErrNotConfigured
|
||||
}
|
||||
|
||||
for !u.S1.HasBits(nxp.UART_S1_TDRE) {
|
||||
gosched()
|
||||
}
|
||||
u.D.Set(c)
|
||||
|
||||
// // wait for room on the buffer
|
||||
// for !u.TXBuffer.Put(c) {
|
||||
// gosched()
|
||||
// }
|
||||
|
||||
// var wrote bool
|
||||
// for u.S1.HasBits(nxp.UART_S1_TDRE) {
|
||||
// n, ok := u.TXBuffer.Get()
|
||||
// if ok {
|
||||
// u.D.Set(n)
|
||||
// wrote = true
|
||||
// } else {
|
||||
// break
|
||||
// }
|
||||
// }
|
||||
|
||||
// if wrote {
|
||||
// u.Transmitting.Set(1)
|
||||
// u.C2.Set(uartC2TXActive)
|
||||
// }
|
||||
return nil
|
||||
}
|
||||
Reference in New Issue
Block a user