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https://github.com/tinygo-org/tinygo.git
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feature: modify i2s interface/implementation to better match specification
Signed-off-by: deadprogram <ron@hybridgroup.com>
This commit is contained in:
deadprogram
+104
-49
@@ -926,23 +926,26 @@ func (i2c *I2C) readByte() byte {
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// I2S
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type I2S struct {
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Bus *sam.I2S_Type
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Bus *sam.I2S_Type
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Frequency uint32
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DataFormat I2SDataFormat
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}
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var I2S0 = I2S{Bus: sam.I2S}
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// Configure is used to configure the I2S interface. You must call this
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// before you can use the I2S bus.
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func (i2s I2S) Configure(config I2SConfig) {
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func (i2s *I2S) Configure(config I2SConfig) error {
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// handle defaults
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if config.SCK == 0 {
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config.SCK = I2S_SCK_PIN
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config.WS = I2S_WS_PIN
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config.SD = I2S_SD_PIN
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config.SDO = I2S_SDO_PIN
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config.SDI = I2S_SDI_PIN
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}
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if config.AudioFrequency == 0 {
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config.AudioFrequency = 48000
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config.AudioFrequency = 44100
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}
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if config.DataFormat == I2SDataFormatDefault {
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@@ -952,39 +955,17 @@ func (i2s I2S) Configure(config I2SConfig) {
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config.DataFormat = I2SDataFormat32bit
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}
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}
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i2s.DataFormat = config.DataFormat
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// Turn on clock for I2S
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sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_I2S_)
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// setting clock rate for sample.
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division_factor := CPUFrequency() / (config.AudioFrequency * uint32(config.DataFormat))
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// Switch Generic Clock Generator 3 to DFLL48M.
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sam.GCLK.GENDIV.Set((sam.GCLK_CLKCTRL_GEN_GCLK3 << sam.GCLK_GENDIV_ID_Pos) |
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(division_factor << sam.GCLK_GENDIV_DIV_Pos))
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waitForSync()
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sam.GCLK.GENCTRL.Set((sam.GCLK_CLKCTRL_GEN_GCLK3 << sam.GCLK_GENCTRL_ID_Pos) |
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(sam.GCLK_GENCTRL_SRC_DFLL48M << sam.GCLK_GENCTRL_SRC_Pos) |
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sam.GCLK_GENCTRL_IDC |
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sam.GCLK_GENCTRL_GENEN)
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waitForSync()
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// Use Generic Clock Generator 3 as source for I2S.
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sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_I2S_0 << sam.GCLK_CLKCTRL_ID_Pos) |
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(sam.GCLK_CLKCTRL_GEN_GCLK3 << sam.GCLK_CLKCTRL_GEN_Pos) |
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sam.GCLK_CLKCTRL_CLKEN)
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waitForSync()
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// reset the device
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i2s.Bus.CTRLA.SetBits(sam.I2S_CTRLA_SWRST)
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for i2s.Bus.SYNCBUSY.HasBits(sam.I2S_SYNCBUSY_SWRST) {
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if err := i2s.SetSampleFrequency(config.AudioFrequency); err != nil {
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return err
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}
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// disable device before continuing
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for i2s.Bus.SYNCBUSY.HasBits(sam.I2S_SYNCBUSY_ENABLE) {
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}
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i2s.Bus.CTRLA.ClearBits(sam.I2S_CTRLA_ENABLE)
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i2s.Enable(false)
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// setup clock
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if config.ClockSource == I2SClockSourceInternal {
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@@ -1067,19 +1048,25 @@ func (i2s I2S) Configure(config I2SConfig) {
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}
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// set serializer mode.
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if config.Mode == I2SModePDM {
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switch config.Mode {
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case I2SModePDM:
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i2s.Bus.SERCTRL1.SetBits(sam.I2S_SERCTRL_SERMODE_PDM2)
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} else {
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case I2SModeSource:
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i2s.Bus.SERCTRL1.SetBits(sam.I2S_SERCTRL_SERMODE_TX)
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case I2SModeReceiver:
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i2s.Bus.SERCTRL1.SetBits(sam.I2S_SERCTRL_SERMODE_RX)
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}
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// configure data pin
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config.SD.Configure(PinConfig{Mode: PinCom})
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// configure data pins
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if config.SDO != NoPin {
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config.SDO.Configure(PinConfig{Mode: PinCom})
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}
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if config.SDI != NoPin {
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config.SDI.Configure(PinConfig{Mode: PinCom})
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}
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// re-enable
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i2s.Bus.CTRLA.SetBits(sam.I2S_CTRLA_ENABLE)
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for i2s.Bus.SYNCBUSY.HasBits(sam.I2S_SYNCBUSY_ENABLE) {
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}
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i2s.Enable(true)
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// enable i2s clock
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i2s.Bus.CTRLA.SetBits(sam.I2S_CTRLA_CKEN0)
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@@ -1090,11 +1077,23 @@ func (i2s I2S) Configure(config I2SConfig) {
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i2s.Bus.CTRLA.SetBits(sam.I2S_CTRLA_SEREN1)
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for i2s.Bus.SYNCBUSY.HasBits(sam.I2S_SYNCBUSY_SEREN1) {
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}
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return nil
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}
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// Read data from the I2S bus into the provided slice.
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// Read mono data from the I2S bus into the provided slice.
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// The I2S bus must already have been configured correctly.
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func (i2s I2S) Read(p []uint32) (n int, err error) {
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func (i2s *I2S) ReadMono(p []uint16) (n int, err error) {
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return i2sRead(i2s, p)
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}
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// Read stereo data from the I2S bus into the provided slice.
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// The I2S bus must already have been configured correctly.
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func (i2s *I2S) ReadStereo(p []uint32) (n int, err error) {
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return i2sRead(i2s, p)
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}
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func i2sRead[T uint16 | uint32](i2s *I2S, p []T) (int, error) {
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i := 0
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for i = 0; i < len(p); i++ {
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// Wait until ready
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@@ -1105,7 +1104,7 @@ func (i2s I2S) Read(p []uint32) (n int, err error) {
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}
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// read data
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p[i] = i2s.Bus.DATA1.Get()
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p[i] = T(i2s.Bus.DATA1.Get())
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// indicate read complete
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i2s.Bus.INTFLAG.Set(sam.I2S_INTFLAG_RXRDY1)
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@@ -1114,9 +1113,19 @@ func (i2s I2S) Read(p []uint32) (n int, err error) {
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return i, nil
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}
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// Write data to the I2S bus from the provided slice.
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// Write mono data to the I2S bus from the provided slice.
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// The I2S bus must already have been configured correctly.
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func (i2s I2S) Write(p []uint32) (n int, err error) {
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func (i2s *I2S) WriteMono(p []uint16) (n int, err error) {
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return i2sWrite(i2s, p)
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}
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// Write stereo data to the I2S bus from the provided slice.
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// The I2S bus must already have been configured correctly.
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func (i2s *I2S) WriteStereo(p []uint32) (n int, err error) {
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return i2sWrite(i2s, p)
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}
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func i2sWrite[T uint16 | uint32](i2s *I2S, p []T) (int, error) {
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i := 0
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for i = 0; i < len(p); i++ {
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// Wait until ready
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@@ -1127,7 +1136,7 @@ func (i2s I2S) Write(p []uint32) (n int, err error) {
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}
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// write data
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i2s.Bus.DATA1.Set(p[i])
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i2s.Bus.DATA1.Set(uint32(p[i]))
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// indicate write complete
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i2s.Bus.INTFLAG.Set(sam.I2S_INTFLAG_TXRDY1)
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@@ -1136,18 +1145,64 @@ func (i2s I2S) Write(p []uint32) (n int, err error) {
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return i, nil
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}
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// Close the I2S bus.
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func (i2s I2S) Close() error {
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// Sync wait
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for i2s.Bus.SYNCBUSY.HasBits(sam.I2S_SYNCBUSY_ENABLE) {
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// SetSampleFrequency is used to set the sample frequency for the I2S bus.
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func (i2s *I2S) SetSampleFrequency(freq uint32) error {
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if freq == 0 {
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return ErrInvalidSampleFrequency
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}
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// disable I2S
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i2s.Bus.CTRLA.ClearBits(sam.I2S_CTRLA_ENABLE)
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if i2s.Frequency == freq {
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return nil
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}
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i2s.Frequency = freq
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// setting clock rate for sample.
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division_factor := CPUFrequency() / (i2s.Frequency * uint32(i2s.DataFormat))
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// Switch Generic Clock Generator 3 to DFLL48M.
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sam.GCLK.GENDIV.Set((sam.GCLK_CLKCTRL_GEN_GCLK3 << sam.GCLK_GENDIV_ID_Pos) |
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(division_factor << sam.GCLK_GENDIV_DIV_Pos))
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waitForSync()
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sam.GCLK.GENCTRL.Set((sam.GCLK_CLKCTRL_GEN_GCLK3 << sam.GCLK_GENCTRL_ID_Pos) |
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(sam.GCLK_GENCTRL_SRC_DFLL48M << sam.GCLK_GENCTRL_SRC_Pos) |
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sam.GCLK_GENCTRL_IDC |
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sam.GCLK_GENCTRL_GENEN)
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waitForSync()
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// Use Generic Clock Generator 3 as source for I2S.
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sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_I2S_0 << sam.GCLK_CLKCTRL_ID_Pos) |
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(sam.GCLK_CLKCTRL_GEN_GCLK3 << sam.GCLK_CLKCTRL_GEN_Pos) |
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sam.GCLK_CLKCTRL_CLKEN)
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waitForSync()
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// reset the device
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i2s.Bus.CTRLA.SetBits(sam.I2S_CTRLA_SWRST)
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for i2s.Bus.SYNCBUSY.HasBits(sam.I2S_SYNCBUSY_SWRST) {
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}
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return nil
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}
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// Enabled is used to enable or disable the I2S bus.
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func (i2s *I2S) Enable(enabled bool) {
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if enabled {
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i2s.Bus.CTRLA.SetBits(sam.I2S_CTRLA_ENABLE)
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for i2s.Bus.SYNCBUSY.HasBits(sam.I2S_SYNCBUSY_ENABLE) {
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}
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return
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}
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// disable
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for i2s.Bus.SYNCBUSY.HasBits(sam.I2S_SYNCBUSY_ENABLE) {
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}
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i2s.Bus.CTRLA.ClearBits(sam.I2S_CTRLA_ENABLE)
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return
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}
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func waitForSync() {
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for sam.GCLK.STATUS.HasBits(sam.GCLK_STATUS_SYNCBUSY) {
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}
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