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device: update SVD files

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This updates lib/cmsis-svd, pulling in the updates to the Espressif SVD
files here:
https://github.com/cmsis-svd/cmsis-svd-data/pull/3

This is needed for wifi/BLE support on the ESP32-C3 (the older SVD files
were missing some necessary interrupts).
This commit is contained in:
Ayke van Laethem
2024-01-30 16:45:24 +01:00
committed by Ron Evans
parent d04b07fa8b
commit 5557e97888
6 changed files with 73 additions and 73 deletions
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src/runtime/runtime_esp32c3.go
+4 -4
View File
@@ -31,12 +31,12 @@ func main() {
esp.TIMG0.WDTCONFIG0.Set(0)
// Disable RTC watchdog.
esp.RTC_CNTL.RTC_WDTWPROTECT.Set(0x50D83AA1)
esp.RTC_CNTL.RTC_WDTCONFIG0.Set(0)
esp.RTC_CNTL.WDTWPROTECT.Set(0x50D83AA1)
esp.RTC_CNTL.WDTCONFIG0.Set(0)
// Disable super watchdog.
esp.RTC_CNTL.RTC_SWD_WPROTECT.Set(0x8F1D312A)
esp.RTC_CNTL.RTC_SWD_CONF.Set(esp.RTC_CNTL_RTC_SWD_CONF_SWD_DISABLE)
esp.RTC_CNTL.SWD_WPROTECT.Set(0x8F1D312A)
esp.RTC_CNTL.SWD_CONF.Set(esp.RTC_CNTL_SWD_CONF_SWD_DISABLE)
// Change CPU frequency from 20MHz to 80MHz, by switching from the XTAL to
// the PLL clock source (see table "CPU Clock Frequency" in the reference
src/runtime/runtime_esp32xx.go
+1 -1
View File
@@ -27,7 +27,7 @@ func initTimer() {
// DIVIDER: 16-bit prescaler, set to 2 for dividing the APB clock by two
// (40MHz).
// esp.TIMG0.T0CONFIG.Set(0 << esp.TIMG_T0CONFIG_T0_EN_Pos)
esp.TIMG0.T0CONFIG.Set(esp.TIMG_T0CONFIG_T0_EN | esp.TIMG_T0CONFIG_T0_INCREASE | 2<<esp.TIMG_T0CONFIG_T0_DIVIDER_Pos)
esp.TIMG0.T0CONFIG.Set(esp.TIMG_T0CONFIG_EN | esp.TIMG_T0CONFIG_INCREASE | 2<<esp.TIMG_T0CONFIG_DIVIDER_Pos)
// esp.TIMG0.T0CONFIG.Set(1 << esp.TIMG_T0CONFIG_T0_DIVCNT_RST_Pos)
// esp.TIMG0.T0CONFIG.Set(esp.TIMG_T0CONFIG_T0_EN)