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all: use unsafe.Add instead of unsafe.Pointer(uintptr(...) + ...)

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We have an optimization for this specific pattern, but it's really just
a hack. With the addition of unsafe.Add in Go 1.17 we can directly
specify the intent instead and eventually remove this special case.

The code is also easier to read.
This commit is contained in:
Ayke van Laethem
2022-12-21 16:14:36 +01:00
committed by Ron Evans
parent d98c0afbab
commit 4ec1e58aa6
29 changed files with 84 additions and 95 deletions
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src/runtime/interrupt/interrupt_esp32c3.go
+2 -2
View File
@@ -34,7 +34,7 @@ func (i Interrupt) Enable() error {
esp.INTERRUPT_CORE0.CPU_INT_TYPE.SetBits(1 << i.num)
// Set default threshold to defaultThreshold
reg := (*volatile.Register32)(unsafe.Pointer((uintptr(unsafe.Pointer(&esp.INTERRUPT_CORE0.CPU_INT_PRI_0)) + uintptr(i.num)*4)))
reg := (*volatile.Register32)(unsafe.Add(unsafe.Pointer(&esp.INTERRUPT_CORE0.CPU_INT_PRI_0), i.num*4))
reg.Set(defaultThreshold)
// Reset interrupt before reenabling
@@ -171,7 +171,7 @@ func handleInterrupt() {
mepc := riscv.MEPC.Get()
// Useing threshold to temporary disable this interrupts.
// FYI: using CPU interrupt enable bit make runtime to loose interrupts.
reg := (*volatile.Register32)(unsafe.Pointer((uintptr(unsafe.Pointer(&esp.INTERRUPT_CORE0.CPU_INT_PRI_0)) + uintptr(interruptNumber)*4)))
reg := (*volatile.Register32)(unsafe.Add(unsafe.Pointer(&esp.INTERRUPT_CORE0.CPU_INT_PRI_0), interruptNumber*4))
thresholdSave := reg.Get()
reg.Set(disableThreshold)
riscv.Asm("fence")