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Add RP2350 support (#4459)
machine/rp2350: add support * add linker scripts for rp2350 * add bootloader * begin melding rp2040 and rp2350 APIs * add UART * add rp2350 boot patching * Fix RP2350 memory layout (#4626) * Remove rp2040-style second stage bootloader. * Add 'minimum viable' IMAGE_DEF embedded block * Create a pico2 specific target * Implement rp2350 init, clock, and uart support * Merge rp2 reset code back together * Separate chip-specific clock definitions * Clear pad isolation bit on rp2350 * Init UART in rp2350 runtime * Correct usb/serial initialization order * Implement jump-to-bootloader * test: add pico2 to smoketests --------- Signed-off-by: deadprogram <ron@hybridgroup.com> Co-authored-by: Matthew Mets <matt.mets@cibomahto.com> Co-authored-by: Matt Mets <matt@blinkinlabs.com> Co-authored-by: deadprogram <ron@hybridgroup.com>
This commit is contained in:
Patricio Whittingslow
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GitHub
GitHub
parent
0d13e61d0c
commit
37f35f8c91
@@ -0,0 +1,199 @@
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//go:build rp2040
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package machine
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import (
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"device/rp"
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"runtime/volatile"
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"unsafe"
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)
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const (
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_NUMBANK0_GPIOS = 30
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_NUMBANK0_IRQS = 4
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_NUMIRQ = 32
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rp2350ExtraReg = 0
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RESETS_RESET_Msk = 0x01ffffff
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initUnreset = rp.RESETS_RESET_ADC |
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rp.RESETS_RESET_RTC |
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rp.RESETS_RESET_SPI0 |
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rp.RESETS_RESET_SPI1 |
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rp.RESETS_RESET_UART0 |
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rp.RESETS_RESET_UART1 |
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rp.RESETS_RESET_USBCTRL
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initDontReset = rp.RESETS_RESET_IO_QSPI |
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rp.RESETS_RESET_PADS_QSPI |
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rp.RESETS_RESET_PLL_USB |
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rp.RESETS_RESET_USBCTRL |
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rp.RESETS_RESET_SYSCFG |
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rp.RESETS_RESET_PLL_SYS
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padEnableMask = rp.PADS_BANK0_GPIO0_IE_Msk |
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rp.PADS_BANK0_GPIO0_OD_Msk
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)
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const (
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PinOutput PinMode = iota
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PinInput
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PinInputPulldown
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PinInputPullup
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PinAnalog
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PinUART
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PinPWM
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PinI2C
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PinSPI
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PinPIO0
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PinPIO1
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)
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const (
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ClkGPOUT0 clockIndex = iota // GPIO Muxing 0
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ClkGPOUT1 // GPIO Muxing 1
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ClkGPOUT2 // GPIO Muxing 2
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ClkGPOUT3 // GPIO Muxing 3
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ClkRef // Watchdog and timers reference clock
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ClkSys // Processors, bus fabric, memory, memory mapped registers
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ClkPeri // Peripheral clock for UART and SPI
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ClkUSB // USB clock
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ClkADC // ADC clock
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ClkRTC // Real time clock
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NumClocks
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)
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func CalcClockDiv(srcFreq, freq uint32) uint32 {
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// Div register is 24.8 int.frac divider so multiply by 2^8 (left shift by 8)
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return uint32((uint64(srcFreq) << 8) / uint64(freq))
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}
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type clocksType struct {
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clk [NumClocks]clockType
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resus struct {
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ctrl volatile.Register32
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status volatile.Register32
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}
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fc0 fc
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wakeEN0 volatile.Register32
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wakeEN1 volatile.Register32
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sleepEN0 volatile.Register32
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sleepEN1 volatile.Register32
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enabled0 volatile.Register32
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enabled1 volatile.Register32
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intR volatile.Register32
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intE volatile.Register32
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intF volatile.Register32
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intS volatile.Register32
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}
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// GPIO function selectors
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const (
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fnJTAG pinFunc = 0
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fnSPI pinFunc = 1 // Connect one of the internal PL022 SPI peripherals to GPIO
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fnUART pinFunc = 2
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fnI2C pinFunc = 3
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// Connect a PWM slice to GPIO. There are eight PWM slices,
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// each with two outputchannels (A/B). The B pin can also be used as an input,
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// for frequency and duty cyclemeasurement
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fnPWM pinFunc = 4
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// Software control of GPIO, from the single-cycle IO (SIO) block.
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// The SIO function (F5)must be selected for the processors to drive a GPIO,
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// but the input is always connected,so software can check the state of GPIOs at any time.
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fnSIO pinFunc = 5
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// Connect one of the programmable IO blocks (PIO) to GPIO. PIO can implement a widevariety of interfaces,
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// and has its own internal pin mapping hardware, allowing flexibleplacement of digital interfaces on bank 0 GPIOs.
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// The PIO function (F6, F7) must beselected for PIO to drive a GPIO, but the input is always connected,
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// so the PIOs canalways see the state of all pins.
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fnPIO0, fnPIO1 pinFunc = 6, 7
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// General purpose clock inputs/outputs. Can be routed to a number of internal clock domains onRP2040,
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// e.g. Input: to provide a 1 Hz clock for the RTC, or can be connected to an internalfrequency counter.
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// e.g. Output: optional integer divide
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fnGPCK pinFunc = 8
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// USB power control signals to/from the internal USB controller
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fnUSB pinFunc = 9
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fnNULL pinFunc = 0x1f
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fnXIP pinFunc = 0
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)
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// Configure configures the gpio pin as per mode.
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func (p Pin) Configure(config PinConfig) {
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if p == NoPin {
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return
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}
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p.init()
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mask := uint32(1) << p
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switch config.Mode {
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case PinOutput:
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p.setFunc(fnSIO)
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rp.SIO.GPIO_OE_SET.Set(mask)
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case PinInput:
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p.setFunc(fnSIO)
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p.pulloff()
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case PinInputPulldown:
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p.setFunc(fnSIO)
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p.pulldown()
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case PinInputPullup:
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p.setFunc(fnSIO)
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p.pullup()
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case PinAnalog:
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p.setFunc(fnNULL)
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p.pulloff()
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case PinUART:
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p.setFunc(fnUART)
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case PinPWM:
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p.setFunc(fnPWM)
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case PinI2C:
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// IO config according to 4.3.1.3 of rp2040 datasheet.
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p.setFunc(fnI2C)
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p.pullup()
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p.setSchmitt(true)
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p.setSlew(false)
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case PinSPI:
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p.setFunc(fnSPI)
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case PinPIO0:
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p.setFunc(fnPIO0)
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case PinPIO1:
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p.setFunc(fnPIO1)
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}
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}
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var (
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timer = (*timerType)(unsafe.Pointer(rp.TIMER))
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)
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// Enable or disable a specific interrupt on the executing core.
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// num is the interrupt number which must be in [0,31].
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func irqSet(num uint32, enabled bool) {
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if num >= _NUMIRQ {
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return
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}
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irqSetMask(1<<num, enabled)
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}
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func irqSetMask(mask uint32, enabled bool) {
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if enabled {
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// Clear pending before enable
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// (if IRQ is actually asserted, it will immediately re-pend)
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rp.PPB.NVIC_ICPR.Set(mask)
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rp.PPB.NVIC_ISER.Set(mask)
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} else {
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rp.PPB.NVIC_ICER.Set(mask)
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}
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}
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func (clks *clocksType) initRTC() {
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// ClkRTC = pllUSB (48MHz) / 1024 = 46875Hz
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clkrtc := clks.clock(ClkRTC)
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clkrtc.configure(0, // No GLMUX
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rp.CLOCKS_CLK_RTC_CTRL_AUXSRC_CLKSRC_PLL_USB,
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48*MHz,
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46875)
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}
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func (clks *clocksType) initTicks() {} // No ticks on RP2040
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// startTick starts the watchdog tick.
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// cycles needs to be a divider that when applied to the xosc input,
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// produces a 1MHz clock. So if the xosc frequency is 12MHz,
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// this will need to be 12.
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func (wd *watchdogImpl) startTick(cycles uint32) {
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rp.WATCHDOG.TICK.Set(cycles | rp.WATCHDOG_TICK_ENABLE)
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}
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