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feat(machine/stm32): add STM32H7 and NUCLEO-H753ZI support
This commit is contained in:
Konstantin Sharlaimov
committed by
Ron Evans
Ron Evans
parent
40ed956d6c
commit
3797e89600
@@ -0,0 +1,179 @@
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//go:build stm32 && stm32h7
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package runtime
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import (
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"device/stm32"
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"machine"
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_ "machine/usb/cdc"
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)
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func init() {
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initCLK()
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initMPU()
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machine.InitSerial()
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initTickTimer(&machine.TIM3)
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}
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func putchar(c byte) {
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machine.Serial.WriteByte(c)
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}
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func getchar() byte {
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for machine.Serial.Buffered() == 0 {
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Gosched()
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}
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v, _ := machine.Serial.ReadByte()
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return v
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}
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func buffered() int {
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return machine.Serial.Buffered()
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}
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func initCLK() {
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// 1. Enable SYSCFG
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stm32.RCC.APB4ENR.SetBits(stm32.RCC_APB4ENR_SYSCFGEN)
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// H743/H753 have no SMPS; the NUCLEO-H753ZI runs VCORE from the internal
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// LDO (the CR3 reset state). Supply bits in CR3 are write-once after POR,
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// so keep LDOEN/BYPASS untouched and only enable the USB 3.3V level
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// detector needed by the USB transceivers.
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stm32.PWR.CR3.SetBits(stm32.PWR_CR3_USB33DEN)
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// 3. Configure VOS1 (Scale 1)
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// RM0433 §6.8.4: ACTVOSRDY must be 1 (Run mode confirmed) before changing VOS.
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for stm32.PWR.CSR1.Get()&stm32.PWR_CSR1_ACTVOSRDY == 0 {
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}
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// RM0433: VOS1 is 0b11.
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stm32.PWR.D3CR.ReplaceBits(0b11<<stm32.PWR_D3CR_VOS_Pos, stm32.PWR_D3CR_VOS_Msk, 0)
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for stm32.PWR.D3CR.Get()&stm32.PWR_D3CR_VOSRDY == 0 {
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}
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// 4. Enable HSE
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if machine.HSEBypass() {
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stm32.RCC.CR.SetBits(stm32.RCC_CR_HSEBYP | stm32.RCC_CR_HSEON)
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} else {
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stm32.RCC.CR.SetBits(stm32.RCC_CR_HSEON)
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}
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for stm32.RCC.CR.Get()&stm32.RCC_CR_HSERDY == 0 {
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}
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// 5. Configure PLL1
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pll := machine.PLLParams400MHz()
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// Source: HSE (2)
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stm32.RCC.PLLCKSELR.ReplaceBits(stm32.RCC_PLLCKSELR_PLLSRC_HSE, stm32.RCC_PLLCKSELR_PLLSRC_Msk, 0)
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// DIVM1
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stm32.RCC.PLLCKSELR.ReplaceBits(pll.M<<stm32.RCC_PLLCKSELR_DIVM1_Pos, stm32.RCC_PLLCKSELR_DIVM1_Msk, 0)
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// PLL1CFGR: Wide VCO (0), Range based on pll.R (VCO input frequency)
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stm32.RCC.PLLCFGR.ReplaceBits(
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(stm32.RCC_PLLCFGR_PLL1VCOSEL_WideVCO<<stm32.RCC_PLLCFGR_PLL1VCOSEL_Pos)|
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(pll.R<<stm32.RCC_PLLCFGR_PLL1RGE_Pos),
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stm32.RCC_PLLCFGR_PLL1VCOSEL_Msk|stm32.RCC_PLLCFGR_PLL1RGE_Msk, 0)
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// PLL1DIVR: DIVN1=pll.N, DIVP1=pll.P, DIVQ1=pll.Q
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// PLL1P = (VCO VCO_input * N) / P
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// PLL1Q = (VCO VCO_input * N) / Q
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stm32.RCC.PLL1DIVR.ReplaceBits(
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(pll.N-1)<<stm32.RCC_PLL1DIVR_DIVN1_Pos|(pll.P-1)<<stm32.RCC_PLL1DIVR_DIVP1_Pos|(pll.Q-1)<<stm32.RCC_PLL1DIVR_DIVQ1_Pos,
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stm32.RCC_PLL1DIVR_DIVN1_Msk|stm32.RCC_PLL1DIVR_DIVP1_Msk|stm32.RCC_PLL1DIVR_DIVQ1_Msk, 0)
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// Enable PLL1P (SYSCLK=400MHz) and PLL1Q (SPI1/2/3 kernel=200MHz)
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stm32.RCC.PLLCFGR.SetBits(stm32.RCC_PLLCFGR_DIVP1EN | stm32.RCC_PLLCFGR_DIVQ1EN)
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// Enable PLL1
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stm32.RCC.CR.SetBits(stm32.RCC_CR_PLL1ON)
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for stm32.RCC.CR.Get()&stm32.RCC_CR_PLL1RDY == 0 {
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}
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// 6. Bus Prescalers
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// D1CPRE=1 (0), HPRE=2 (8) -> HCLK=200MHz, D1PPRE (APB3)=2 (4) -> PCLK3=100MHz
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stm32.RCC.D1CFGR.ReplaceBits(
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(stm32.RCC_D1CFGR_D1CPRE_Div1<<stm32.RCC_D1CFGR_D1CPRE_Pos)|
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(stm32.RCC_D1CFGR_HPRE_Div2<<stm32.RCC_D1CFGR_HPRE_Pos)|
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(stm32.RCC_D1CFGR_D1PPRE_Div2<<stm32.RCC_D1CFGR_D1PPRE_Pos),
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stm32.RCC_D1CFGR_D1CPRE_Msk|stm32.RCC_D1CFGR_HPRE_Msk|stm32.RCC_D1CFGR_D1PPRE_Msk, 0)
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// D2CFGR: D2PPRE1 (APB1)=2 (4) -> PCLK1=100MHz, D2PPRE2 (APB2)=2 (4) -> PCLK2=100MHz
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stm32.RCC.D2CFGR.ReplaceBits(
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(stm32.RCC_D2CFGR_D2PPRE1_Div2<<stm32.RCC_D2CFGR_D2PPRE1_Pos)|
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(stm32.RCC_D2CFGR_D2PPRE2_Div2<<stm32.RCC_D2CFGR_D2PPRE2_Pos),
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stm32.RCC_D2CFGR_D2PPRE1_Msk|stm32.RCC_D2CFGR_D2PPRE2_Msk, 0)
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// D3CFGR: D3PPRE (APB4)=2 (4) -> PCLK4=100MHz
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stm32.RCC.D3CFGR.ReplaceBits(
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stm32.RCC_D3CFGR_D3PPRE_Div2<<stm32.RCC_D3CFGR_D3PPRE_Pos,
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stm32.RCC_D3CFGR_D3PPRE_Msk, 0)
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// 7. Flash Latency
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// VOS1, 200MHz AXI clock -> 2 wait states, WRHIGHFREQ=2 (RM0433 Table 17).
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stm32.FLASH.ACR.ReplaceBits(2|2<<stm32.FLASH_ACR_WRHIGHFREQ_Pos,
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stm32.FLASH_ACR_LATENCY_Msk|stm32.FLASH_ACR_WRHIGHFREQ_Msk, 0)
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for stm32.FLASH.ACR.Get()&stm32.FLASH_ACR_LATENCY_Msk != 2 {
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}
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// 8. Switch to PLL1
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// SW: PLL1 (3)
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stm32.RCC.CFGR.ReplaceBits(3<<stm32.RCC_CFGR_SW_Pos, stm32.RCC_CFGR_SW_Msk, 0)
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for (stm32.RCC.CFGR.Get() & stm32.RCC_CFGR_SWS_Msk) != (3 << stm32.RCC_CFGR_SWS_Pos) {
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}
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// 9. Peripheral Kernel Clocks
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// I2C1,2,3 source: HSI_KER (2) to keep 64MHz timing compatibility.
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stm32.RCC.D2CCIP2R.ReplaceBits(stm32.RCC_D2CCIP2R_I2C123SEL_HSI_KER<<stm32.RCC_D2CCIP2R_I2C123SEL_Pos, stm32.RCC_D2CCIP2R_I2C123SEL_Msk, 0)
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// I2C4 source: HSI_KER (2)
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stm32.RCC.D3CCIPR.ReplaceBits(stm32.RCC_D3CCIPR_I2C4SEL_HSI_KER<<stm32.RCC_D3CCIPR_I2C4SEL_Pos, stm32.RCC_D3CCIPR_I2C4SEL_Msk, 0)
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// SPI1,2,3 source: PLL1_Q (0) -> 200MHz
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stm32.RCC.D2CCIP1R.ReplaceBits(stm32.RCC_D2CCIP1R_SPI123SEL_PLL1_Q<<stm32.RCC_D2CCIP1R_SPI123SEL_Pos, stm32.RCC_D2CCIP1R_SPI123SEL_Msk, 0)
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// SPI4,5 source: APB (0) -> PCLK2 = 100MHz (PLL1-derived)
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stm32.RCC.D2CCIP1R.ReplaceBits(stm32.RCC_D2CCIP1R_SPI45SEL_APB<<stm32.RCC_D2CCIP1R_SPI45SEL_Pos, stm32.RCC_D2CCIP1R_SPI45SEL_Msk, 0)
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// SPI6 source: PCLK4 (0) -> 100MHz (PLL1-derived)
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stm32.RCC.D3CCIPR.ReplaceBits(stm32.RCC_D3CCIPR_SPI6SEL_RCC_PCLK4<<stm32.RCC_D3CCIPR_SPI6SEL_Pos, stm32.RCC_D3CCIPR_SPI6SEL_Msk, 0)
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// 10. HSI48 — used as kernel clock for RNG and USB (RM0433 §33.3 requires ≤48 MHz).
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stm32.RCC.CR.SetBits(stm32.RCC_CR_HSI48ON)
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for stm32.RCC.CR.Get()&stm32.RCC_CR_HSI48RDY == 0 {
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}
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// RNGSEL and USBSEL reset value is 0x0 (HSI48 or PLL1_Q); set explicitly to HSI48.
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stm32.RCC.D2CCIP2R.ReplaceBits(
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stm32.RCC_D2CCIP2R_RNGSEL_HSI48<<stm32.RCC_D2CCIP2R_RNGSEL_Pos|
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stm32.RCC_D2CCIP2R_USBSEL_HSI48<<stm32.RCC_D2CCIP2R_USBSEL_Pos,
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stm32.RCC_D2CCIP2R_RNGSEL_Msk|stm32.RCC_D2CCIP2R_USBSEL_Msk, 0)
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// 11. Enable CRS (Clock Recovery System) for HSI48 stabilization via USB SOF.
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stm32.RCC.APB1HENR.SetBits(stm32.RCC_APB1HENR_CRSEN)
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stm32.CRS.CFGR.ReplaceBits(stm32.CRS_CFGR_SYNCSRC_USB_SOF<<stm32.CRS_CFGR_SYNCSRC_Pos, stm32.CRS_CFGR_SYNCSRC_Msk, 0)
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stm32.CRS.CR.SetBits(stm32.CRS_CR_CEN | stm32.CRS_CR_AUTOTRIMEN)
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// 12. Configure PLL2 for ADC (80MHz)
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// DIVM2 = pll.M
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stm32.RCC.PLLCKSELR.ReplaceBits(pll.M<<stm32.RCC_PLLCKSELR_DIVM2_Pos, stm32.RCC_PLLCKSELR_DIVM2_Msk, 0)
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// PLL2CFGR: Wide VCO (0), Range based on pll.R (VCO input frequency)
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stm32.RCC.PLLCFGR.ReplaceBits(
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(stm32.RCC_PLLCFGR_PLL2VCOSEL_WideVCO<<stm32.RCC_PLLCFGR_PLL2VCOSEL_Pos)|
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(pll.R<<stm32.RCC_PLLCFGR_PLL2RGE_Pos),
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stm32.RCC_PLLCFGR_PLL2VCOSEL_Msk|stm32.RCC_PLLCFGR_PLL2RGE_Msk, 0)
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// PLL2DIVR: DIVN2=pll.N, DIVP2=10 (Value 9)
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// PLL2P = (VCO VCO_input * N) / 10 = 80MHz
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stm32.RCC.PLL2DIVR.ReplaceBits(
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(pll.N-1)<<stm32.RCC_PLL2DIVR_DIVN2_Pos|9<<stm32.RCC_PLL2DIVR_DIVP2_Pos,
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stm32.RCC_PLL2DIVR_DIVN2_Msk|stm32.RCC_PLL2DIVR_DIVP2_Msk, 0)
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// Enable DIVP2EN
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stm32.RCC.PLLCFGR.SetBits(stm32.RCC_PLLCFGR_DIVP2EN)
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// Enable PLL2
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stm32.RCC.CR.SetBits(stm32.RCC_CR_PLL2ON)
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for stm32.RCC.CR.Get()&stm32.RCC_CR_PLL2RDY == 0 {
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}
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// 12. ADC kernel clock source: PLL2_P (0).
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stm32.RCC.D3CCIPR.ReplaceBits(stm32.RCC_D3CCIPR_ADCSEL_PLL2_P<<stm32.RCC_D3CCIPR_ADCSEL_Pos, stm32.RCC_D3CCIPR_ADCSEL_Msk, 0)
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}
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@@ -0,0 +1,128 @@
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//go:build stm32 && stm32h7
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package runtime
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import (
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"device/arm"
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"runtime/volatile"
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"unsafe"
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)
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// Cortex-M7 cache size registers (ARM TRM Table 4-2, within SCB address space).
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var (
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scbCCSIDR = (*volatile.Register32)(unsafe.Pointer(uintptr(0xE000ED80))) // Cache Size ID Register (R)
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scbCSELR = (*volatile.Register32)(unsafe.Pointer(uintptr(0xE000ED84))) // Cache Size Selection Register (R/W)
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)
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// Cortex-M7 cache maintenance registers (ARMv7-M Architecture Ref Manual Table B3-7).
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var (
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scbICIALLU = (*volatile.Register32)(unsafe.Pointer(uintptr(0xE000EF50))) // Invalidate all I-cache (W)
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scbDCISW = (*volatile.Register32)(unsafe.Pointer(uintptr(0xE000EF60))) // Invalidate D-cache by set/way (W)
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)
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// RASR region attribute presets for this chip's memory map (ARMv7-M
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// Architecture Ref Manual §B3.5.5). The register layout itself
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// (arm.MPU_Type, arm.MPU_RASR_* field positions) is generic to any
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// ARMv7-M core (M3/M4/M7) and lives in device/arm; only these specific
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// size/type/permission combinations are STM32H7-specific.
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const (
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// SIZE field bits[5:1]: value = log2(region_bytes) - 1.
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mpuRASRSize2MB = 20 << arm.MPU_RASR_SIZE_Pos // 2MB = 2^21, field=20
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mpuRASRSize512KB = 18 << arm.MPU_RASR_SIZE_Pos // 512KB = 2^19, field=18
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mpuRASRSize512MB = 28 << arm.MPU_RASR_SIZE_Pos // 512MB = 2^29, field=28
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// AP field bits[26:24].
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mpuRASRAPReadOnly = 0x6 << arm.MPU_RASR_AP_Pos // Privileged and unprivileged read-only
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mpuRASRAPFullAccess = 0x3 << arm.MPU_RASR_AP_Pos // Full access (privileged and unprivileged)
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// Memory type encodings: TEX bits[21:19], S bit[18], C bit[17], B bit[16].
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// Normal, Write-Through, No Write-Allocate (TEX=000, C=1, B=0, S=0).
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mpuRASRNormalWT = arm.MPU_RASR_C
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// Normal, Write-Back, Write-Allocate (TEX=001, C=1, B=1, S=0).
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mpuRASRNormalWBWA = (1 << arm.MPU_RASR_TEX_Pos) | arm.MPU_RASR_C | arm.MPU_RASR_B
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// Shared Device memory (TEX=000, C=0, B=1, S=1).
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mpuRASRDevice = arm.MPU_RASR_S | arm.MPU_RASR_B
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)
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// initMPU configures the Cortex-M7 MPU, then enables L1 instruction and data
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// caches. Must be called after initCLK() and before any peripheral access.
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//
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// Memory map configured:
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//
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// Region 0: Flash 0x08000000 2MB Normal WT, RO, executable
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// Region 1: AXI SRAM 0x24000000 512KB Normal WBWA, RW, no-execute
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// Region 2: Peripherals 0x40000000 512MB Shared Device, RW, no-execute
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//
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// Unmapped regions fall back to the ARMv7-M default privileged map via
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// PRIVDEFENA, keeping NVIC/SCB and other PPB accesses strongly-ordered.
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func initMPU() {
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// Disable MPU before reconfiguring regions.
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arm.MPU.CTRL.Set(0)
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arm.Asm("dsb 0xF")
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arm.Asm("isb 0xF")
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// Region 0: Flash — Normal, Write-Through, read-only, executable.
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arm.MPU.RNR.Set(0)
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arm.MPU.RBAR.Set(0x08000000)
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arm.MPU.RASR.Set(mpuRASRNormalWT | mpuRASRAPReadOnly | mpuRASRSize2MB | arm.MPU_RASR_ENABLE)
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// Region 1: AXI SRAM — Normal, Write-Back Write-Allocate, full access, no-execute.
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arm.MPU.RNR.Set(1)
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arm.MPU.RBAR.Set(0x24000000)
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arm.MPU.RASR.Set(arm.MPU_RASR_XN | mpuRASRNormalWBWA | mpuRASRAPFullAccess | mpuRASRSize512KB | arm.MPU_RASR_ENABLE)
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// Region 2: Peripherals — Shared Device, full access, no-execute.
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arm.MPU.RNR.Set(2)
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arm.MPU.RBAR.Set(0x40000000)
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arm.MPU.RASR.Set(arm.MPU_RASR_XN | mpuRASRDevice | mpuRASRAPFullAccess | mpuRASRSize512MB | arm.MPU_RASR_ENABLE)
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// Enable MemManage fault so MPU violations raise a MemFault rather than
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// hard-faulting directly.
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arm.SCB.SHCSR.SetBits(arm.SCB_SHCSR_MEMFAULTENA)
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// Enable MPU with privileged default background map.
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arm.MPU.CTRL.Set(arm.MPU_CTRL_ENABLE | arm.MPU_CTRL_PRIVDEFENA)
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arm.Asm("dsb 0xF")
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arm.Asm("isb 0xF")
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// Enable L1 caches now that the MPU defines cacheability for each region.
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initICache()
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initDCache()
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}
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// initICache invalidates then enables the L1 instruction cache.
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func initICache() {
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arm.Asm("dsb 0xF")
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arm.Asm("isb 0xF")
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scbICIALLU.Set(0) // Invalidate all I-cache lines.
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arm.Asm("dsb 0xF")
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arm.Asm("isb 0xF")
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arm.SCB.CCR.SetBits(arm.SCB_CCR_IC)
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arm.Asm("dsb 0xF")
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arm.Asm("isb 0xF")
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}
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// initDCache invalidates all D-cache lines by set/way then enables the cache.
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// Iterates over sets and ways read from CCSIDR so it works for any M7 cache
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// size (8–64 KB, always 4-way, 32-byte lines on STM32H743).
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func initDCache() {
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scbCSELR.Set(0) // Select L1 D-cache.
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arm.Asm("dsb 0xF")
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ccsidr := scbCCSIDR.Get()
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numSets := (ccsidr >> 13) & 0x7FFF // NUMSETS field (value = sets-1)
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assoc := (ccsidr >> 3) & 0x3FF // ASSOCIATIVITY field (value = ways-1)
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// Invalidate every set/way. For a 4-way cache the way index occupies
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// bits[31:30] of DCISW; the set index starts at bit 5 (32-byte line = 2^5).
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for set := uint32(0); set <= numSets; set++ {
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for way := uint32(0); way <= assoc; way++ {
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scbDCISW.Set((way << 30) | (set << 5))
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}
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}
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arm.Asm("dsb 0xF")
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arm.SCB.CCR.SetBits(arm.SCB_CCR_DC)
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arm.Asm("dsb 0xF")
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arm.Asm("isb 0xF")
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}
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