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machine/nrf52840+nxpmk66f18: rename files to match naming format for all other boards/machines
Signed-off-by: deadprogram <ron@hybridgroup.com>
This commit is contained in:
deadprogram
@@ -0,0 +1,303 @@
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// Derivative work of Teensyduino Core Library
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// http://www.pjrc.com/teensy/
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// Copyright (c) 2017 PJRC.COM, LLC.
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//
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// Permission is hereby granted, free of charge, to any person obtaining
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// a copy of this software and associated documentation files (the
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// "Software"), to deal in the Software without restriction, including
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// without limitation the rights to use, copy, modify, merge, publish,
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// distribute, sublicense, and/or sell copies of the Software, and to
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// permit persons to whom the Software is furnished to do so, subject to
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// the following conditions:
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//
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// 1. The above copyright notice and this permission notice shall be
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// included in all copies or substantial portions of the Software.
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//
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// 2. If the Software is incorporated into a build system that allows
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// selection among a list of target devices, then similar target
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// devices manufactured by PJRC.COM must be included in the list of
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// target devices and selectable in the same manner.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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// +build nxp,mk66f18
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package machine
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import (
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"device/arm"
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"device/nxp"
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"errors"
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"runtime/interrupt"
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"runtime/volatile"
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_ "unsafe" // for go:linkname
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)
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const (
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uartC2Enable = nxp.UART_C2_TE | nxp.UART_C2_RE | nxp.UART_C2_RIE | nxp.UART_C2_ILIE
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uartC2TXActive = uartC2Enable | nxp.UART_C2_TIE
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uartC2TXCompleting = uartC2Enable | nxp.UART_C2_TCIE
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uartC2TXInactive = uartC2Enable
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uartIRQPriority = 64
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// determined from UARTx_PFIFO
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uartRXFIFODepth = 8
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uartTXFIFODepth = 8
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)
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var (
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ErrNotImplemented = errors.New("device has not been implemented")
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ErrNotConfigured = errors.New("device has not been configured")
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)
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//go:linkname gosched runtime.Gosched
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func gosched()
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// PutcharUART writes a byte to the UART synchronously, without using interrupts
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// or calling the scheduler
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func PutcharUART(u *UART, c byte) {
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// ensure the UART has been configured
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if !u.SCGC.HasBits(u.SCGCMask) {
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u.configure(UARTConfig{}, false)
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}
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for u.TCFIFO.Get() > 0 {
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// busy wait
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}
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u.D.Set(c)
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u.C2.Set(uartC2TXActive)
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}
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// PollUART manually checks a UART status and calls the ISR. This should only be
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// called by runtime.abort.
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func PollUART(u *UART) {
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if u.SCGC.HasBits(u.SCGCMask) {
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u.handleStatusInterrupt(u.Interrupt)
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}
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}
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type UART struct {
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*nxp.UART_Type
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SCGC *volatile.Register32
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SCGCMask uint32
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DefaultRX Pin
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DefaultTX Pin
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// state
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Buffer RingBuffer // RX Buffer
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TXBuffer RingBuffer
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Configured bool
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Transmitting volatile.Register8
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Interrupt interrupt.Interrupt
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}
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var UART0 = UART{UART_Type: nxp.UART0, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART0, DefaultRX: defaultUART0RX, DefaultTX: defaultUART0TX}
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var UART1 = UART{UART_Type: nxp.UART1, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART1, DefaultRX: defaultUART1RX, DefaultTX: defaultUART1TX}
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var UART2 = UART{UART_Type: nxp.UART2, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART2, DefaultRX: defaultUART2RX, DefaultTX: defaultUART2TX}
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var UART3 = UART{UART_Type: nxp.UART3, SCGC: &nxp.SIM.SCGC4, SCGCMask: nxp.SIM_SCGC4_UART3, DefaultRX: defaultUART3RX, DefaultTX: defaultUART3TX}
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var UART4 = UART{UART_Type: nxp.UART4, SCGC: &nxp.SIM.SCGC1, SCGCMask: nxp.SIM_SCGC1_UART4, DefaultRX: defaultUART4RX, DefaultTX: defaultUART4TX}
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func init() {
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UART0.Interrupt = interrupt.New(nxp.IRQ_UART0_RX_TX, UART0.handleStatusInterrupt)
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UART1.Interrupt = interrupt.New(nxp.IRQ_UART1_RX_TX, UART1.handleStatusInterrupt)
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UART2.Interrupt = interrupt.New(nxp.IRQ_UART2_RX_TX, UART2.handleStatusInterrupt)
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UART3.Interrupt = interrupt.New(nxp.IRQ_UART3_RX_TX, UART3.handleStatusInterrupt)
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UART4.Interrupt = interrupt.New(nxp.IRQ_UART4_RX_TX, UART4.handleStatusInterrupt)
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}
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// Configure the UART.
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func (u *UART) Configure(config UARTConfig) {
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u.configure(config, true)
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}
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func (u *UART) configure(config UARTConfig, canSched bool) {
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// from: serial_begin
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if !u.Configured {
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u.Transmitting.Set(0)
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// turn on the clock
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u.SCGC.Set(u.SCGCMask)
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// configure pins
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u.DefaultRX.Control().Set(nxp.PORT_PCR0_PE | nxp.PORT_PCR0_PS | nxp.PORT_PCR0_PFE | (3 << nxp.PORT_PCR0_MUX_Pos))
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u.DefaultTX.Control().Set(nxp.PORT_PCR0_DSE | nxp.PORT_PCR0_SRE | (3 << nxp.PORT_PCR0_MUX_Pos))
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u.C1.Set(nxp.UART_C1_ILT)
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}
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// default to 115200 baud
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if config.BaudRate == 0 {
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config.BaudRate = 115200
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}
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// copied from teensy core's BAUD2DIV macro
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divisor := ((CPUFrequency() * 2) + (config.BaudRate >> 1)) / config.BaudRate
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if divisor < 32 {
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divisor = 32
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}
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if u.Configured {
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// don't change baud rate mid transmit
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if canSched {
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u.Flush()
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} else {
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for u.Transmitting.Get() != 0 {
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// busy wait flush
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}
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}
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}
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// set the divisor
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u.BDH.Set(uint8((divisor >> 13) & 0x1F))
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u.BDL.Set(uint8((divisor >> 5) & 0xFF))
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u.C4.Set(uint8(divisor & 0x1F))
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if !u.Configured {
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u.Configured = true
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u.C1.Set(nxp.UART_C1_ILT)
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// configure TX and RX watermark
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u.TWFIFO.Set(2) // causes bit TDRE of S1 to set
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u.RWFIFO.Set(4) // causes bit RDRF of S1 to set
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// enable FIFOs
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u.PFIFO.Set(nxp.UART_PFIFO_TXFE | nxp.UART_PFIFO_RXFE)
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// setup interrupts
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u.C2.Set(uartC2TXInactive)
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u.Interrupt.SetPriority(uartIRQPriority)
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u.Interrupt.Enable()
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}
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}
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func (u *UART) Disable() {
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// from: serial_end
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// check if the device has been enabled already
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if !u.SCGC.HasBits(u.SCGCMask) {
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return
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}
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u.Flush()
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u.Interrupt.Disable()
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u.C2.Set(0)
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// reconfigure pin
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u.DefaultRX.Configure(PinConfig{Mode: PinInputPullUp})
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u.DefaultTX.Configure(PinConfig{Mode: PinInputPullUp})
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// clear flags
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u.S1.Get()
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u.D.Get()
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u.Buffer.Clear()
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}
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func (u *UART) Flush() {
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for u.Transmitting.Get() != 0 {
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gosched()
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}
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}
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func (u *UART) handleStatusInterrupt(interrupt.Interrupt) {
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// from: uart0_status_isr
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// receive
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if u.S1.HasBits(nxp.UART_S1_RDRF | nxp.UART_S1_IDLE) {
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intrs := arm.DisableInterrupts()
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avail := u.RCFIFO.Get()
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if avail == 0 {
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// The only way to clear the IDLE interrupt flag is
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// to read the data register. But reading with no
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// data causes a FIFO underrun, which causes the
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// FIFO to return corrupted data. If anyone from
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// Freescale reads this, what a poor design! There
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// write should be a write-1-to-clear for IDLE.
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u.D.Get()
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// flushing the fifo recovers from the underrun,
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// but there's a possible race condition where a
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// new character could be received between reading
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// RCFIFO == 0 and flushing the FIFO. To minimize
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// the chance, interrupts are disabled so a higher
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// priority interrupt (hopefully) doesn't delay.
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// TODO: change this to disabling the IDLE interrupt
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// which won't be simple, since we already manage
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// which transmit interrupts are enabled.
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u.CFIFO.Set(nxp.UART_CFIFO_RXFLUSH)
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arm.EnableInterrupts(intrs)
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} else {
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arm.EnableInterrupts(intrs)
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for {
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u.Buffer.Put(u.D.Get())
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avail--
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if avail <= 0 {
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break
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}
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}
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}
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}
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// transmit
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if u.C2.HasBits(nxp.UART_C2_TIE) && u.S1.HasBits(nxp.UART_S1_TDRE) {
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data := make([]byte, 0, uartTXFIFODepth)
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avail := uartTXFIFODepth - u.TCFIFO.Get()
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// get avail bytes from ring buffer
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for len(data) < int(avail) {
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if b, ok := u.TXBuffer.Get(); ok {
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data = append(data, b)
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} else {
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break
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}
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}
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// write data to FIFO
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l := len(data)
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for i, b := range data {
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if i == l-1 {
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// only clear TDRE on last write, per the manual
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u.S1.Get()
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}
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u.D.Set(b)
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}
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// if FIFO still has room, disable TIE, enable TCIE
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if u.S1.HasBits(nxp.UART_S1_TDRE) {
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u.C2.Set(uartC2TXCompleting)
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}
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}
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// transmit complete
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if u.C2.HasBits(nxp.UART_C2_TCIE) && u.S1.HasBits(nxp.UART_S1_TC) {
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u.Transmitting.Set(0)
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u.C2.Set(uartC2TXInactive)
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}
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}
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// WriteByte writes a byte of data to the UART.
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func (u *UART) WriteByte(c byte) error {
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if !u.Configured {
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return ErrNotConfigured
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}
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for !u.TXBuffer.Put(c) {
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gosched()
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}
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u.Transmitting.Set(1)
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u.C2.Set(uartC2TXActive)
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return nil
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}
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