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Code Issues Packages Projects Releases 6 Wiki Activity

risc-v: add support for 64-bit RISC-V CPUs

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This commit is contained in:
Yannis Huber
2020-06-08 16:47:39 +02:00
committed by GitHub
parent d61d5d7ab1
commit 2396c22658
8 changed files with 100 additions and 8 deletions
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tools/gen-device-svd/gen-device-svd.go
+4
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@@ -681,6 +681,8 @@ var (
var regType string
switch register.elementSize {
case 8:
regType = "volatile.Register64"
case 4:
regType = "volatile.Register32"
case 2:
@@ -710,6 +712,8 @@ var (
for _, subregister := range register.registers {
var subregType string
switch subregister.elementSize {
case 8:
subregType = "volatile.Register64"
case 4:
subregType = "volatile.Register32"
case 2: