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add STM32F405 machine/runtime, and new board/target feather-stm32f405
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ardnew
Ron Evans
@@ -0,0 +1,237 @@
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// +build stm32,stm32f4,stm32f405
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package runtime
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import (
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"device/arm"
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"device/stm32"
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"runtime/interrupt"
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"runtime/volatile"
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)
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func init() {
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initOSC() // configure oscillators
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initCLK() // configure CPU, AHB, and APB bus clocks
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initTIM() // configure timers
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}
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const (
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HCLK_FREQ_HZ = 168000000
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PCLK1_FREQ_HZ = HCLK_FREQ_HZ / 4
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PCLK2_FREQ_HZ = HCLK_FREQ_HZ / 2
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)
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const (
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PWR_SCALE1 = 1 << stm32.PWR_CSR_VOSRDY_Pos // max value of HCLK = 168 MHz
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PWR_SCALE2 = 0 // max value of HCLK = 144 MHz
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PLL_SRC_HSE = 1 << stm32.RCC_PLLCFGR_PLLSRC_Pos // use HSE for PLL and PLLI2S
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PLL_SRC_HSI = 0 // use HSI for PLL and PLLI2S
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PLL_DIV_M = 6 << stm32.RCC_PLLCFGR_PLLM0_Pos
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PLL_MLT_N = 168 << stm32.RCC_PLLCFGR_PLLN0_Pos
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PLL_DIV_P = ((2 >> 1) - 1) << stm32.RCC_PLLCFGR_PLLP0_Pos
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PLL_DIV_Q = 7 << stm32.RCC_PLLCFGR_PLLQ0_Pos
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SYSCLK_SRC_PLL = 2 << stm32.RCC_CFGR_SW0_Pos
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RCC_DIV_PCLK1 = 5 << stm32.RCC_CFGR_PPRE1_Pos // HCLK / 4
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RCC_DIV_PCLK2 = 4 << stm32.RCC_CFGR_PPRE2_Pos // HCLK / 2
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RCC_DIV_HCLK = 0 << stm32.RCC_CFGR_HPRE_Pos // SYSCLK / 1
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CLK_CCM_RAM = 1 << 20
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)
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const (
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// +---------------------+---------------------------------------------------------------------------+
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// | | HCLK (MHz) |
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// | +------------------+------------------+------------------+------------------+
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// | Wait states (WS) | Voltage range | Voltage range | Voltage range | Voltage range |
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// | (LATENCY) | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
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// | | | | | Prefetch OFF |
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// +---------------------+------------------+------------------+------------------+------------------+
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// | 0 WS (1 CPU cycle) | 0 < HCLK ≤ 30 | 0 < HCLK ≤ 24 | 0 < HCLK ≤ 22 | 0 < HCLK ≤ 20 |
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// | 1 WS (2 CPU cycles) | 30 < HCLK ≤ 60 | 24 < HCLK ≤ 48 | 22 < HCLK ≤ 44 | 20 < HCLK ≤ 40 |
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// | 2 WS (3 CPU cycles) | 60 < HCLK ≤ 90 | 48 < HCLK ≤ 72 | 44 < HCLK ≤ 66 | 40 < HCLK ≤ 60 |
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// | 3 WS (4 CPU cycles) | 90 < HCLK ≤ 120 | 72 < HCLK ≤ 96 | 66 < HCLK ≤ 88 | 60 < HCLK ≤ 80 |
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// | 4 WS (5 CPU cycles) | 120 < HCLK ≤ 150 | 96 < HCLK ≤ 120 | 88 < HCLK ≤ 110 | 80 < HCLK ≤ 100 |
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// | 5 WS (6 CPU cycles) | 150 < HCLK ≤ 168 | 120 < HCLK ≤ 144 | 110 < HCLK ≤ 132 | 100 < HCLK ≤ 120 |
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// | 6 WS (7 CPU cycles) | | 144 < HCLK ≤ 168 | 132 < HCLK ≤ 154 | 120 < HCLK ≤ 140 |
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// | 7 WS (8 CPU cycles) | | | 154 < HCLK ≤ 168 | 140 < HCLK ≤ 160 |
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// +---------------------+------------------+------------------+------------------+------------------+
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FLASH_LATENCY = 5 << stm32.FLASH_ACR_LATENCY_Pos // 5 WS (6 CPU cycles)
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// instruction cache, data cache, and prefetch
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FLASH_OPTIONS = stm32.FLASH_ACR_ICEN | stm32.FLASH_ACR_DCEN | stm32.FLASH_ACR_PRFTEN
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)
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/*
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clock settings
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+-------------+--------+
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| HSE | 12mhz |
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| SYSCLK | 168mhz |
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| HCLK | 168mhz |
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| APB1(PCLK1) | 42mhz |
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| APB2(PCLK2) | 84mhz |
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+-------------+--------+
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*/
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func initOSC() {
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// enable voltage regulator
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN)
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stm32.PWR.CR.SetBits(PWR_SCALE1)
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// enable HSE
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stm32.RCC.CR.Set(stm32.RCC_CR_HSEON)
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for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSERDY) {
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}
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// Since the main-PLL configuration parameters cannot be changed once PLL is
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// enabled, it is recommended to configure PLL before enabling it (selection
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// of the HSI or HSE oscillator as PLL clock source, and configuration of
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// division factors M, N, P, and Q).
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// disable PLL and wait for it to reset
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stm32.RCC.CR.ClearBits(stm32.RCC_CR_PLLON)
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for stm32.RCC.CR.HasBits(stm32.RCC_CR_PLLRDY) {
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}
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// set HSE as PLL source and configure clock divisors
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stm32.RCC.PLLCFGR.Set(PLL_SRC_HSE | PLL_DIV_M | PLL_MLT_N | PLL_DIV_P | PLL_DIV_Q)
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// enable PLL and wait for it to sync
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stm32.RCC.CR.SetBits(stm32.RCC_CR_PLLON)
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for !stm32.RCC.CR.HasBits(stm32.RCC_CR_PLLRDY) {
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}
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}
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func initCLK() {
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// After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is
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// configured in the FLASH_ACR register.
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//
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// It is highly recommended to use the following software sequences to tune
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// the number of wait states needed to access the Flash memory with the CPU
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// frequency.
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//
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// 1. Program the new number of wait states to the LATENCY bits in the
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// FLASH_ACR register
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// 2. Check that the new number of wait states is taken into account to access
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// the Flash memory by reading the FLASH_ACR register
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// 3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR
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// register
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// 4. If needed, modify the CPU clock prescaler by writing the HPRE bits in
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// RCC_CFGR
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// 5. Check that the new CPU clock source or/and the new CPU clock prescaler
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// value is/are taken into account by reading the clock source status (SWS
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// bits) or/and the AHB prescaler value (HPRE bits), respectively, in the
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// RCC_CFGR register.
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// configure instruction/data caching, prefetch, and flash access wait states
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stm32.FLASH.ACR.Set(FLASH_OPTIONS | FLASH_LATENCY)
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// After a system reset, the HSI oscillator is selected as the system clock.
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// When a clock source is used directly or through PLL as the system clock, it
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// is not possible to stop it.
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//
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// A switch from one clock source to another occurs only if the target clock
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// source is ready (clock stable after startup delay or PLL locked). If a
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// clock source that is not yet ready is selected, the switch occurs when the
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// clock source is ready. Status bits in the RCC clock control register
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// (RCC_CR) indicate which clock(s) is (are) ready and which clock is
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// currently used as the system clock.
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// set CPU clock source to PLL
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stm32.RCC.CFGR.SetBits(SYSCLK_SRC_PLL)
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for !stm32.RCC.CFGR.HasBits(SYSCLK_SRC_PLL) {
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}
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// update PCKL1/2 and HCLK divisors
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stm32.RCC.CFGR.SetBits(RCC_DIV_PCLK1 | RCC_DIV_PCLK2 | RCC_DIV_HCLK)
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// enable the CCM RAM clock
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stm32.RCC.AHB1ENR.SetBits(CLK_CCM_RAM)
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}
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func initTIM() {
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// enable sleep counter (TIM3)
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM3EN)
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tim3 := interrupt.New(stm32.IRQ_TIM3, handleTIM3)
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tim3.SetPriority(0xC3)
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tim3.Enable()
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// enable tick counter (TIM7)
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM7EN)
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stm32.TIM7.PSC.Set((PCLK1_FREQ_HZ*2)/10000 - 1) // 84mhz to 10khz(0.1ms)
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stm32.TIM7.ARR.Set(10 - 1) // interrupt per 1ms
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stm32.TIM7.DIER.SetBits(stm32.TIM_DIER_UIE) // enable interrupt
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stm32.TIM7.CR1.SetBits(stm32.TIM_CR1_CEN) // enable timer
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tim7 := interrupt.New(stm32.IRQ_TIM7, handleTIM7)
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tim7.SetPriority(0xC1)
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tim7.Enable()
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}
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var (
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// tick in milliseconds
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tickCount timeUnit
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timerWakeup volatile.Register8
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)
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const asyncScheduler = false
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func ticksToNanoseconds(ticks timeUnit) int64 {
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return int64(ticks) * 1000
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}
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func nanosecondsToTicks(ns int64) timeUnit {
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return timeUnit(ns / 1000)
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}
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// sleepTicks should sleep for specific number of microseconds.
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func sleepTicks(d timeUnit) {
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timerSleep(uint32(d))
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}
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// number of ticks (microseconds) since start.
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func ticks() timeUnit {
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return tickCount * 1000 // milliseconds to microseconds
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}
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// ticks are in microseconds
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func timerSleep(ticks uint32) {
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timerWakeup.Set(0)
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stm32.TIM3.PSC.Set((PCLK1_FREQ_HZ*2)/10000 - 1) // 8399
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arr := (ticks / 100) - 1 // convert from microseconds to 0.1 ms
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if arr == 0 {
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arr = 1 // avoid blocking
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}
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stm32.TIM3.ARR.Set(arr)
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stm32.TIM3.DIER.SetBits(stm32.TIM_DIER_UIE) // enable interrupt
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stm32.TIM3.CR1.SetBits(stm32.TIM_CR1_CEN) // enable the timer
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// wait for timer
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for timerWakeup.Get() == 0 {
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arm.Asm("wfi")
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}
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}
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func handleTIM3(interrupt.Interrupt) {
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if stm32.TIM3.SR.HasBits(stm32.TIM_SR_UIF) {
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stm32.TIM3.CR1.ClearBits(stm32.TIM_CR1_CEN) // disable the timer
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stm32.TIM3.SR.ClearBits(stm32.TIM_SR_UIF) // clear the update flag
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timerWakeup.Set(1) // flag timer ISR
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}
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}
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func handleTIM7(interrupt.Interrupt) {
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if stm32.TIM7.SR.HasBits(stm32.TIM_SR_UIF) {
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stm32.TIM7.SR.ClearBits(stm32.TIM_SR_UIF) // clear the update flag
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tickCount++
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}
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}
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func putchar(c byte) {}
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