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teensy40: refactor to remove unnecessary code and constants
This commit is contained in:
ardnew
Ron Evans
@@ -6,66 +6,13 @@ import (
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"device/nxp"
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)
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// Core, bus, and peripheral clock frequencies (Hz)
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// Core clock frequencies (Hz)
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const (
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CORE_FREQ = 600000000 // 600 MHz
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SYSTICK_FREQ = 100000 // 100 kHz (see note below)
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_ // -----------
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AHB_FREQ = 600000000 // 600 MHz
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CAN_FREQ = 40000000 // 40 MHz
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CKIL_SYNC_FREQ = 32768 // 32.768 kHz
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CSI_FREQ = 12000000 // 12 MHz
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FLEXIO1_FREQ = 30000000 // 30 MHz
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FLEXIO2_FREQ = 30000000 // 30 MHz
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FLEXSPI2_FREQ = 327724137 // 327.7 MHz
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FLEXSPI_FREQ = 327724137 // 327.7 MHz
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IPG_FREQ = 150000000 // 150 MHz
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LCDIF_FREQ = 39272727 // 39.3 MHz
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LPI2C_FREQ = 60000000 // 60 MHz
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LPSPI_FREQ = 132000000 // 132 MHz
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PERCLK_FREQ = 24000000 // 24 MHz
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SAI1_FREQ = 63529411 // 63.5 MHz
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SAI2_FREQ = 63529411 // 63.5 MHz
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SAI3_FREQ = 63529411 // 63.5 MHz
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SEMC_FREQ = 163862068 // 163.9 MHz
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SPDIF0_FREQ = 30000000 // 30 MHz
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TRACE_FREQ = 132000000 // 132 MHz
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UART_FREQ = 24000000 // 24 MHz
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USDHC1_FREQ = 198000000 // 198 MHz
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USDHC2_FREQ = 198000000 // 198 MHz
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CORE_FREQ = 600000000 // 600 MHz
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OSC_FREQ = 24000000 // 24 MHz
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)
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var (
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ArmPllConfig = nxp.ClockConfigArmPll{
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LoopDivider: 100, // PLL loop divider, Fout = Fin * 50
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Src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N
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}
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SysPllConfig = nxp.ClockConfigSysPll{
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LoopDivider: 1, // PLL loop divider, Fout = Fin * ( 20 + LoopDivider*2 + Numerator / Denominator )
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Numerator: 0, // 30 bit Numerator of fractional loop divider
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Denominator: 1, // 30 bit Denominator of fractional loop divider
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Src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N
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}
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Usb1PllConfig = nxp.ClockConfigUsbPll{
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Instance: 1, // USB PLL Instance
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LoopDivider: 0, // PLL loop divider, Fout = Fin * 20
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Src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N
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}
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Usb2PllConfig = nxp.ClockConfigUsbPll{
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Instance: 2, // USB PLL Instance
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LoopDivider: 0, // PLL loop divider, Fout = Fin * 20
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Src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N
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}
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VideoPllConfig = nxp.ClockConfigVideoPll{
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LoopDivider: 31, // PLL loop divider, Fout = Fin * ( LoopDivider + Numerator / Denominator )
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PostDivider: 8, // Divider after PLL
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Numerator: 0, // 30 bit Numerator of fractional loop divider, Fout = Fin * ( LoopDivider + Numerator / Denominator )
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Denominator: 1, // 30 bit Denominator of fractional loop divider, Fout = Fin * ( LoopDivider + Numerator / Denominator )
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Src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N
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}
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)
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// Note about SYSTICK_FREQ from Teensyduino (cores/teensy4/startup.c):
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// Note from Teensyduino (cores/teensy4/startup.c):
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//
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// | ARM SysTick is used for most Ardiuno timing functions, delay(), millis(),
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// | micros(). SysTick can run from either the ARM core clock, or from an
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@@ -75,6 +22,30 @@ var (
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// | the external clock is really 100 kHz. We use this clock rather than the
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// | ARM clock, to allow SysTick to maintain correct timing even when we change
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// | the ARM clock to run at different speeds.
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const SYSTICK_FREQ = 100000 // 100 kHz
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var (
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ArmPllConfig = nxp.ClockConfigArmPll{
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LoopDivider: 100, // PLL loop divider, Fout=Fin*50
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Src: 0, // bypass clock source, 0=OSC24M, 1=CLK1_P & CLK1_N
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}
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SysPllConfig = nxp.ClockConfigSysPll{
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LoopDivider: 1, // PLL loop divider, Fout=Fin*(20+LOOP*2+NUMER/DENOM)
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Numerator: 0, // 30-bit NUMER of fractional loop divider
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Denominator: 1, // 30-bit DENOM of fractional loop divider
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Src: 0, // bypass clock source, 0=OSC24M, 1=CLK1_P & CLK1_N
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}
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Usb1PllConfig = nxp.ClockConfigUsbPll{
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Instance: 1, // USB PLL instance
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LoopDivider: 0, // PLL loop divider, Fout=Fin*20
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Src: 0, // bypass clock source, 0=OSC24M, 1=CLK1_P & CLK1_N
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}
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Usb2PllConfig = nxp.ClockConfigUsbPll{
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Instance: 2, // USB PLL instance
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LoopDivider: 0, // PLL loop divider, Fout=Fin*20
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Src: 0, // bypass clock source, 0=OSC24M, 1=CLK1_P & CLK1_N
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}
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)
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// initClocks configures the core, buses, and all peripherals' clock source mux
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// and dividers for runtime. The clock gates for individual peripherals are all
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@@ -85,11 +56,10 @@ func initClocks() {
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// disable low-power mode so that __WFI doesn't lock up at runtime.
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// see: Using the MIMXRT1060/4-EVK with MCUXpresso IDE v10.3.x (v1.0.2,
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// 2019MAR01), chapter 14
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nxp.ModeClkRun.Set()
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nxp.ClockModeRun.Set()
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// enable 1MHz clock output
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// enable and use 1MHz clock output
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nxp.XTALOSC24M.OSC_CONFIG2.SetBits(nxp.XTALOSC24M_OSC_CONFIG2_ENABLE_1M_Msk)
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// use free 1MHz clock output
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nxp.XTALOSC24M.OSC_CONFIG2.ClearBits(nxp.XTALOSC24M_OSC_CONFIG2_MUX_1M_Msk)
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// initialize external 24 MHz clock
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@@ -101,10 +71,8 @@ func initClocks() {
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}
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nxp.CCM_ANALOG.MISC0_CLR.Set(nxp.CCM_ANALOG_MISC0_OSC_XTALOK_EN_Msk)
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// initialize internal RC oscillator 24 MHz clock
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// initialize internal RC OSC 24 MHz, and switch clock source to external OSC
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nxp.XTALOSC24M.LOWPWR_CTRL.SetBits(nxp.XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_Msk)
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// switch clock source to external oscillator
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nxp.XTALOSC24M.LOWPWR_CTRL_CLR.Set(nxp.XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_Msk)
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// set oscillator ready counter value
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@@ -123,142 +91,122 @@ func initClocks() {
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for !nxp.DCDC.REG0.HasBits(nxp.DCDC_REG0_STS_DC_OK_Msk) {
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}
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// -------------------------------------------------------------------- AHB --
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nxp.DivIpAhb.Div(0) // divide AHB_PODF (DIV1)
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// -------------------------------------------------------------------- ADC --
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nxp.ClockIpAdc1.Enable(false) // disable ADC clock gates
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nxp.ClockIpAdc2.Enable(false) // ~
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nxp.ClockIpAdc1.Enable(false) // disable ADC
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nxp.ClockIpAdc2.Enable(false) //
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// ------------------------------------------------------------------- XBAR --
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nxp.ClockIpXbar1.Enable(false) // disable XBAR clock gates
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nxp.ClockIpXbar2.Enable(false) // ~
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nxp.ClockIpXbar3.Enable(false) // ~
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nxp.ClockIpXbar1.Enable(false) // disable XBAR
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nxp.ClockIpXbar2.Enable(false) //
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nxp.ClockIpXbar3.Enable(false) //
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// ---------------------------------------------------------------- ARM/IPG --
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nxp.DivIpIpg.Div(3) // divide IPG_PODF (DIV4)
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nxp.DivIpArm.Div(1) // divide ARM_PODF (DIV2)
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nxp.DivIpPeriphClk2.Div(0) // divide PERIPH_CLK2_PODF (DIV1)
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// ---------------------------------------------------------------- GPT/PIT --
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nxp.ClockIpGpt1.Enable(false) // disable GPT/PIT clock gates
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nxp.ClockIpGpt1S.Enable(false) // ~
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nxp.ClockIpGpt2.Enable(false) // ~
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nxp.ClockIpGpt2S.Enable(false) // ~
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nxp.ClockIpPit.Enable(false) // ~
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nxp.ClockIpGpt1.Enable(false) // disable GPT/PIT
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nxp.ClockIpGpt1S.Enable(false) //
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nxp.ClockIpGpt2.Enable(false) //
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nxp.ClockIpGpt2S.Enable(false) //
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nxp.ClockIpPit.Enable(false) //
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// -------------------------------------------------------------------- PER --
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nxp.DivIpPerclk.Div(0) // divide PERCLK_PODF (DIV1)
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// ------------------------------------------------------------------ USDHC --
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nxp.ClockIpUsdhc1.Enable(false) // disable USDHC1 clock gate
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nxp.ClockIpUsdhc1.Enable(false) // disable USDHC1
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nxp.DivIpUsdhc1.Div(1) // divide USDHC1_PODF (DIV2)
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nxp.MuxIpUsdhc1.Mux(1) // USDHC1 select PLL2_PFD0
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nxp.ClockIpUsdhc2.Enable(false) // disable USDHC2 clock gate
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nxp.ClockIpUsdhc2.Enable(false) // disable USDHC2
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nxp.DivIpUsdhc2.Div(1) // divide USDHC2_PODF (DIV2)
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nxp.MuxIpUsdhc2.Mux(1) // USDHC2 select PLL2_PFD0
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// ------------------------------------------------------------------- SEMC --
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nxp.ClockIpSemc.Enable(false) // disable SEMC clock gate
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nxp.ClockIpSemc.Enable(false) // disable SEMC
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nxp.DivIpSemc.Div(1) // divide SEMC_PODF (DIV2)
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nxp.MuxIpSemcAlt.Mux(0) // SEMC_ALT select PLL2_PFD2
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nxp.MuxIpSemc.Mux(1) // SEMC select SEMC_ALT
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// ---------------------------------------------------------------- FLEXSPI --
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if false {
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// TODO: external flash is on this bus, configured via DCD block
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nxp.ClockIpFlexSpi.Enable(false) // disable FLEXSPI clock gate
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nxp.ClockIpFlexSpi.Enable(false) // disable FLEXSPI
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nxp.DivIpFlexSpi.Div(0) // divide FLEXSPI_PODF (DIV1)
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nxp.MuxIpFlexSpi.Mux(2) // FLEXSPI select PLL2_PFD2
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}
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nxp.ClockIpFlexSpi2.Enable(false) // disable FLEXSPI2 clock gate
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nxp.ClockIpFlexSpi2.Enable(false) // disable FLEXSPI2
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nxp.DivIpFlexSpi2.Div(0) // divide FLEXSPI2_PODF (DIV1)
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nxp.MuxIpFlexSpi2.Mux(0) // FLEXSPI2 select PLL2_PFD2
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// -------------------------------------------------------------------- CSI --
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nxp.ClockIpCsi.Enable(false) // disable CSI clock gate
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nxp.ClockIpCsi.Enable(false) // disable CSI
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nxp.DivIpCsi.Div(1) // divide CSI_PODF (DIV2)
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nxp.MuxIpCsi.Mux(0) // CSI select OSC24M
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// ------------------------------------------------------------------ LPSPI --
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nxp.ClockIpLpspi1.Enable(false) // disable LPSPI clock gate
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nxp.ClockIpLpspi2.Enable(false) // ~
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nxp.ClockIpLpspi3.Enable(false) // ~
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nxp.ClockIpLpspi4.Enable(false) // ~
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nxp.ClockIpLpspi1.Enable(false) // disable LPSPI
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nxp.ClockIpLpspi2.Enable(false) //
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nxp.ClockIpLpspi3.Enable(false) //
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nxp.ClockIpLpspi4.Enable(false) //
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nxp.DivIpLpspi.Div(3) // divide LPSPI_PODF (DIV4)
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nxp.MuxIpLpspi.Mux(2) // LPSPI select PLL2
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// ------------------------------------------------------------------ TRACE --
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nxp.ClockIpTrace.Enable(false) // disable TRACE clock gate
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nxp.ClockIpTrace.Enable(false) // disable TRACE
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nxp.DivIpTrace.Div(3) // divide TRACE_PODF (DIV4)
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nxp.MuxIpTrace.Mux(0) // TRACE select PLL2_MAIN
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// -------------------------------------------------------------------- SAI --
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nxp.ClockIpSai1.Enable(false) // disable SAI1 clock gate
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nxp.ClockIpSai1.Enable(false) // disable SAI1
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nxp.DivIpSai1Pre.Div(3) // divide SAI1_CLK_PRED (DIV4)
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nxp.DivIpSai1.Div(1) // divide SAI1_CLK_PODF (DIV2)
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nxp.MuxIpSai1.Mux(0) // SAI1 select PLL3_PFD2
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nxp.ClockIpSai2.Enable(false) // disable SAI2 clock gate
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nxp.ClockIpSai2.Enable(false) // disable SAI2
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nxp.DivIpSai2Pre.Div(3) // divide SAI2_CLK_PRED (DIV4)
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nxp.DivIpSai2.Div(1) // divide SAI2_CLK_PODF (DIV2)
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nxp.MuxIpSai2.Mux(0) // SAI2 select PLL3_PFD2
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nxp.ClockIpSai3.Enable(false) // disable SAI3 clock gate
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nxp.ClockIpSai3.Enable(false) // disable SAI3
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nxp.DivIpSai3Pre.Div(3) // divide SAI3_CLK_PRED (DIV4)
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nxp.DivIpSai3.Div(1) // divide SAI3_CLK_PODF (DIV2)
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nxp.MuxIpSai3.Mux(0) // SAI3 select PLL3_PFD2
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// ------------------------------------------------------------------ LPI2C --
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nxp.ClockIpLpi2c1.Enable(false) // disable LPI2C clock gate
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nxp.ClockIpLpi2c2.Enable(false) // ~
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nxp.ClockIpLpi2c3.Enable(false) // ~
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nxp.ClockIpLpi2c1.Enable(false) // disable LPI2C
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nxp.ClockIpLpi2c2.Enable(false) //
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nxp.ClockIpLpi2c3.Enable(false) //
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nxp.DivIpLpi2c.Div(0) // divide LPI2C_CLK_PODF (DIV1)
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nxp.MuxIpLpi2c.Mux(0) // LPI2C select PLL3_SW_60M
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// -------------------------------------------------------------------- CAN --
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nxp.ClockIpCan1.Enable(false) // disable CAN clock gate
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nxp.ClockIpCan2.Enable(false) // ~
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nxp.ClockIpCan3.Enable(false) // ~
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nxp.ClockIpCan1S.Enable(false) // ~
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nxp.ClockIpCan2S.Enable(false) // ~
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nxp.ClockIpCan3S.Enable(false) // ~
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nxp.ClockIpCan1.Enable(false) // disable CAN
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nxp.ClockIpCan2.Enable(false) //
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nxp.ClockIpCan3.Enable(false) //
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nxp.ClockIpCan1S.Enable(false) //
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nxp.ClockIpCan2S.Enable(false) //
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nxp.ClockIpCan3S.Enable(false) //
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nxp.DivIpCan.Div(1) // divide CAN_CLK_PODF (DIV2)
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nxp.MuxIpCan.Mux(2) // CAN select PLL3_SW_80M
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// ------------------------------------------------------------------- UART --
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nxp.ClockIpLpuart1.Enable(false) // disable UART clock gate
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nxp.ClockIpLpuart2.Enable(false) // ~
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nxp.ClockIpLpuart3.Enable(false) // ~
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nxp.ClockIpLpuart4.Enable(false) // ~
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nxp.ClockIpLpuart5.Enable(false) // ~
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nxp.ClockIpLpuart6.Enable(false) // ~
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nxp.ClockIpLpuart7.Enable(false) // ~
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nxp.ClockIpLpuart8.Enable(false) // ~
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nxp.ClockIpLpuart1.Enable(false) // disable UART
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nxp.ClockIpLpuart2.Enable(false) //
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nxp.ClockIpLpuart3.Enable(false) //
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nxp.ClockIpLpuart4.Enable(false) //
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nxp.ClockIpLpuart5.Enable(false) //
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nxp.ClockIpLpuart6.Enable(false) //
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nxp.ClockIpLpuart7.Enable(false) //
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nxp.ClockIpLpuart8.Enable(false) //
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nxp.DivIpUart.Div(0) // divide UART_CLK_PODF (DIV1)
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nxp.MuxIpUart.Mux(1) // UART select OSC
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// -------------------------------------------------------------------- LCD --
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nxp.ClockIpLcdPixel.Enable(false) // disable LCDIF clock gate
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nxp.ClockIpLcdPixel.Enable(false) // disable LCDIF
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nxp.DivIpLcdifPre.Div(1) // divide LCDIF_PRED (DIV2)
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nxp.DivIpLcdif.Div(3) // divide LCDIF_CLK_PODF (DIV4)
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nxp.MuxIpLcdifPre.Mux(5) // LCDIF_PRE select PLL3_PFD1
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// ------------------------------------------------------------------ SPDIF --
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nxp.ClockIpSpdif.Enable(false) // disable SPDIF clock gate
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nxp.ClockIpSpdif.Enable(false) // disable SPDIF
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nxp.DivIpSpdif0Pre.Div(1) // divide SPDIF0_CLK_PRED (DIV2)
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nxp.DivIpSpdif0.Div(7) // divide SPDIF0_CLK_PODF (DIV8)
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nxp.MuxIpSpdif.Mux(3) // SPDIF select PLL3_SW
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// ----------------------------------------------------------------- FLEXIO --
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nxp.ClockIpFlexio1.Enable(false) // disable FLEXIO1 clock gate
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nxp.ClockIpFlexio1.Enable(false) // disable FLEXIO1
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nxp.DivIpFlexio1Pre.Div(1) // divide FLEXIO1_CLK_PRED (DIV2)
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nxp.DivIpFlexio1.Div(7) // divide FLEXIO1_CLK_PODF (DIV8)
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nxp.MuxIpFlexio1.Mux(3) // FLEXIO1 select PLL3_SW
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nxp.ClockIpFlexio2.Enable(false) // enable FLEXIO2 clock gate
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nxp.ClockIpFlexio2.Enable(false) // disable FLEXIO2
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nxp.DivIpFlexio2Pre.Div(1) // divide FLEXIO2_CLK_PRED (DIV2)
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nxp.DivIpFlexio2.Div(7) // divide FLEXIO2_CLK_PODF (DIV8)
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nxp.MuxIpFlexio2.Mux(3) // FLEXIO2 select PLL3_SW
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// ---------------------------------------------------------------- PLL/PFD --
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nxp.MuxIpPll3Sw.Mux(0) // PLL3_SW select PLL3_MAIN
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ArmPllConfig.Configure() // init ARM PLL
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@@ -277,18 +225,15 @@ func initClocks() {
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Usb1PllConfig.Configure() // init USB1 PLL and PFDs
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Usb2PllConfig.Configure() // init USB2 PLL
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// --------------------------------------------------------------- ARM CORE --
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nxp.MuxIpPrePeriph.Mux(3) // PRE_PERIPH select ARM_PLL
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nxp.MuxIpPeriph.Mux(0) // PERIPH select PRE_PERIPH
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nxp.MuxIpPeriphClk2.Mux(1) // PERIPH_CLK2 select OSC
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nxp.MuxIpPerclk.Mux(1) // PERCLK select OSC
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// ------------------------------------------------------------------- LVDS --
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// set LVDS1 clock source
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nxp.CCM_ANALOG.MISC1.Set((nxp.CCM_ANALOG.MISC1.Get() & ^uint32(nxp.CCM_ANALOG_MISC1_LVDS1_CLK_SEL_Msk)) |
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((0 << nxp.CCM_ANALOG_MISC1_LVDS1_CLK_SEL_Pos) & nxp.CCM_ANALOG_MISC1_LVDS1_CLK_SEL_Msk))
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// ----------------------------------------------------------------- CLKOUT --
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// set CLOCK_OUT1 divider
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nxp.CCM.CCOSR.Set((nxp.CCM.CCOSR.Get() & ^uint32(nxp.CCM_CCOSR_CLKO1_DIV_Msk)) |
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((0 << nxp.CCM_CCOSR_CLKO1_DIV_Pos) & nxp.CCM_CCOSR_CLKO1_DIV_Msk))
|
||||
@@ -306,95 +251,80 @@ func initClocks() {
|
||||
nxp.CCM.CCOSR.SetBits(nxp.CCM_CCOSR_CLKO1_EN_Msk) // enable CLK_OUT1
|
||||
nxp.CCM.CCOSR.SetBits(nxp.CCM_CCOSR_CLKO2_EN_Msk) // enable CLK_OUT2
|
||||
|
||||
// ----------------------------------------------------------------- IOMUXC --
|
||||
nxp.ClockIpIomuxcGpr.Enable(false) // disable IOMUXC_GPR clock gate
|
||||
nxp.ClockIpIomuxc.Enable(false) // disable IOMUXC clock gate
|
||||
nxp.ClockIpIomuxcGpr.Enable(false) // disable IOMUXC_GPR
|
||||
nxp.ClockIpIomuxc.Enable(false) // disable IOMUXC
|
||||
// set GPT1 High frequency reference clock source
|
||||
nxp.IOMUXC_GPR.GPR5.ClearBits(nxp.IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_Msk)
|
||||
// set GPT2 High frequency reference clock source
|
||||
nxp.IOMUXC_GPR.GPR5.ClearBits(nxp.IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_Msk)
|
||||
|
||||
// ------------------------------------------------------------------- GPIO --
|
||||
nxp.ClockIpGpio1.Enable(false) // disable GPIO clock gates
|
||||
nxp.ClockIpGpio2.Enable(false) // ~
|
||||
nxp.ClockIpGpio3.Enable(false) // ~
|
||||
nxp.ClockIpGpio4.Enable(false) // ~
|
||||
nxp.ClockIpGpio1.Enable(false) // disable GPIO
|
||||
nxp.ClockIpGpio2.Enable(false) //
|
||||
nxp.ClockIpGpio3.Enable(false) //
|
||||
nxp.ClockIpGpio4.Enable(false) //
|
||||
}
|
||||
|
||||
func enableTimerClocks() {
|
||||
|
||||
// ---------------------------------------------------------------- GPT/PIT --
|
||||
nxp.ClockIpGpt1.Enable(true) // enable GPT/PIT clock gates
|
||||
nxp.ClockIpGpt1S.Enable(true) // ~
|
||||
nxp.ClockIpGpt2.Enable(true) // ~
|
||||
nxp.ClockIpGpt2S.Enable(true) // ~
|
||||
nxp.ClockIpPit.Enable(true) // ~
|
||||
nxp.ClockIpGpt1.Enable(true) // enable GPT/PIT
|
||||
nxp.ClockIpGpt1S.Enable(true) //
|
||||
nxp.ClockIpGpt2.Enable(true) //
|
||||
nxp.ClockIpGpt2S.Enable(true) //
|
||||
nxp.ClockIpPit.Enable(true) //
|
||||
}
|
||||
|
||||
func enablePinClocks() {
|
||||
|
||||
// ----------------------------------------------------------------- IOMUXC --
|
||||
nxp.ClockIpIomuxcGpr.Enable(true) // enable IOMUXC clock gates
|
||||
nxp.ClockIpIomuxc.Enable(true) // ~
|
||||
nxp.ClockIpIomuxcGpr.Enable(true) // enable IOMUXC
|
||||
nxp.ClockIpIomuxc.Enable(true) //
|
||||
|
||||
// ------------------------------------------------------------------- GPIO --
|
||||
nxp.ClockIpGpio1.Enable(true) // enable GPIO clock gates
|
||||
nxp.ClockIpGpio2.Enable(true) // ~
|
||||
nxp.ClockIpGpio3.Enable(true) // ~
|
||||
nxp.ClockIpGpio4.Enable(true) // ~
|
||||
nxp.ClockIpGpio1.Enable(true) // enable GPIO
|
||||
nxp.ClockIpGpio2.Enable(true) //
|
||||
nxp.ClockIpGpio3.Enable(true) //
|
||||
nxp.ClockIpGpio4.Enable(true) //
|
||||
}
|
||||
|
||||
func enablePeripheralClocks() {
|
||||
|
||||
// -------------------------------------------------------------------- ADC --
|
||||
nxp.ClockIpAdc1.Enable(true) // enable ADC clock gates
|
||||
nxp.ClockIpAdc2.Enable(true) // ~
|
||||
nxp.ClockIpAdc1.Enable(true) // enable ADC
|
||||
nxp.ClockIpAdc2.Enable(true) //
|
||||
|
||||
// ------------------------------------------------------------------- XBAR --
|
||||
nxp.ClockIpXbar1.Enable(true) // enable XBAR clock gates
|
||||
nxp.ClockIpXbar2.Enable(true) // ~
|
||||
nxp.ClockIpXbar3.Enable(true) // ~
|
||||
nxp.ClockIpXbar1.Enable(true) // enable XBAR
|
||||
nxp.ClockIpXbar2.Enable(true) //
|
||||
nxp.ClockIpXbar3.Enable(true) //
|
||||
|
||||
// ------------------------------------------------------------------ USDHC --
|
||||
nxp.ClockIpUsdhc1.Enable(true) // enable USDHC clock gates
|
||||
nxp.ClockIpUsdhc2.Enable(true) // ~
|
||||
nxp.ClockIpUsdhc1.Enable(true) // enable USDHC
|
||||
nxp.ClockIpUsdhc2.Enable(true) //
|
||||
|
||||
// ------------------------------------------------------------------- SEMC --
|
||||
nxp.ClockIpSemc.Enable(true) // enable SEMC clock gate
|
||||
nxp.ClockIpSemc.Enable(true) // enable SEMC
|
||||
|
||||
// ---------------------------------------------------------------- FLEXSPI --
|
||||
nxp.ClockIpFlexSpi2.Enable(true) // enable FLEXSPI2 clock gate
|
||||
nxp.ClockIpFlexSpi2.Enable(true) // enable FLEXSPI2
|
||||
|
||||
// ------------------------------------------------------------------ LPSPI --
|
||||
nxp.ClockIpLpspi1.Enable(true) // enable LPSPI clock gate
|
||||
nxp.ClockIpLpspi2.Enable(true) // ~
|
||||
nxp.ClockIpLpspi3.Enable(true) // ~
|
||||
nxp.ClockIpLpspi4.Enable(true) // ~
|
||||
nxp.ClockIpLpspi1.Enable(true) // enable LPSPI
|
||||
nxp.ClockIpLpspi2.Enable(true) //
|
||||
nxp.ClockIpLpspi3.Enable(true) //
|
||||
nxp.ClockIpLpspi4.Enable(true) //
|
||||
|
||||
// ------------------------------------------------------------------ LPI2C --
|
||||
nxp.ClockIpLpi2c1.Enable(true) // enable LPI2C clock gate
|
||||
nxp.ClockIpLpi2c2.Enable(true) // ~
|
||||
nxp.ClockIpLpi2c3.Enable(true) // ~
|
||||
nxp.ClockIpLpi2c1.Enable(true) // enable LPI2C
|
||||
nxp.ClockIpLpi2c2.Enable(true) //
|
||||
nxp.ClockIpLpi2c3.Enable(true) //
|
||||
|
||||
// -------------------------------------------------------------------- CAN --
|
||||
nxp.ClockIpCan1.Enable(true) // enable CAN clock gate
|
||||
nxp.ClockIpCan2.Enable(true) // ~
|
||||
nxp.ClockIpCan3.Enable(true) // ~
|
||||
nxp.ClockIpCan1S.Enable(true) // ~
|
||||
nxp.ClockIpCan2S.Enable(true) // ~
|
||||
nxp.ClockIpCan3S.Enable(true) // ~
|
||||
nxp.ClockIpCan1.Enable(true) // enable CAN
|
||||
nxp.ClockIpCan2.Enable(true) //
|
||||
nxp.ClockIpCan3.Enable(true) //
|
||||
nxp.ClockIpCan1S.Enable(true) //
|
||||
nxp.ClockIpCan2S.Enable(true) //
|
||||
nxp.ClockIpCan3S.Enable(true) //
|
||||
|
||||
// ------------------------------------------------------------------- UART --
|
||||
nxp.ClockIpLpuart1.Enable(true) // enable UART clock gate
|
||||
nxp.ClockIpLpuart2.Enable(true) // ~
|
||||
nxp.ClockIpLpuart3.Enable(true) // ~
|
||||
nxp.ClockIpLpuart4.Enable(true) // ~
|
||||
nxp.ClockIpLpuart5.Enable(true) // ~
|
||||
nxp.ClockIpLpuart6.Enable(true) // ~
|
||||
nxp.ClockIpLpuart7.Enable(true) // ~
|
||||
nxp.ClockIpLpuart8.Enable(true) // ~
|
||||
nxp.ClockIpLpuart1.Enable(true) // enable UART
|
||||
nxp.ClockIpLpuart2.Enable(true) //
|
||||
nxp.ClockIpLpuart3.Enable(true) //
|
||||
nxp.ClockIpLpuart4.Enable(true) //
|
||||
nxp.ClockIpLpuart5.Enable(true) //
|
||||
nxp.ClockIpLpuart6.Enable(true) //
|
||||
nxp.ClockIpLpuart7.Enable(true) //
|
||||
nxp.ClockIpLpuart8.Enable(true) //
|
||||
|
||||
// ----------------------------------------------------------------- FLEXIO --
|
||||
nxp.ClockIpFlexio1.Enable(true) // enable FLEXIO clock gates
|
||||
nxp.ClockIpFlexio2.Enable(true) // ~
|
||||
nxp.ClockIpFlexio1.Enable(true) // enable FLEXIO
|
||||
nxp.ClockIpFlexio2.Enable(true) //
|
||||
}
|
||||
|
||||
@@ -10,50 +10,38 @@ func initCache() {
|
||||
|
||||
nxp.MPU.Enable(false)
|
||||
|
||||
// -------------------------------------------------------- OVERLAY REGIONS --
|
||||
|
||||
// add Default [0] region to deny access to whole address space to workaround
|
||||
// speculative prefetch. Refer to Arm errata 1013783-B for more details.
|
||||
|
||||
// [0] Default {OVERLAY}:
|
||||
// 4 GiB, -access, @device, -exec, -share, -cache, -buffer, -subregion
|
||||
// [0] Default {OVERLAY}: 4 GiB, -access, @device, -exec, -share, -cache, -buffer, -subregion
|
||||
nxp.MPU.SetRBAR(0, 0x00000000)
|
||||
nxp.MPU.SetRASR(nxp.RGNSZ_4GB, nxp.PERM_NONE, nxp.EXTN_DEVICE, false, false, false, false, false)
|
||||
|
||||
// [1] Peripherals {OVERLAY}:
|
||||
// 64 MiB, +ACCESS, @device, +EXEC, -share, -cache, -buffer, -subregion
|
||||
// [1] Peripherals {OVERLAY}: 64 MiB, +ACCESS, @device, +EXEC, -share, -cache, -buffer, -subregion
|
||||
nxp.MPU.SetRBAR(1, 0x40000000)
|
||||
nxp.MPU.SetRASR(nxp.RGNSZ_64MB, nxp.PERM_FULL, nxp.EXTN_DEVICE, true, false, false, false, false)
|
||||
|
||||
// [2] RAM {OVERLAY}:
|
||||
// 1 GiB, +ACCESS, @device, +EXEC, -share, -cache, -buffer, -subregion
|
||||
// [2] RAM {OVERLAY}: 1 GiB, +ACCESS, @device, +EXEC, -share, -cache, -buffer, -subregion
|
||||
nxp.MPU.SetRBAR(2, 0x00000000)
|
||||
nxp.MPU.SetRASR(nxp.RGNSZ_1GB, nxp.PERM_FULL, nxp.EXTN_DEVICE, true, false, false, false, false)
|
||||
|
||||
// ----------------------------------------------------- PERIPHERAL REGIONS --
|
||||
|
||||
// [3] ITCM:
|
||||
// 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, -cache, -buffer, -subregion
|
||||
// [3] ITCM: 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, -cache, -buffer, -subregion
|
||||
nxp.MPU.SetRBAR(3, 0x00000000)
|
||||
nxp.MPU.SetRASR(nxp.RGNSZ_512KB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, false, false, false)
|
||||
|
||||
// [4] DTCM:
|
||||
// 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, -cache, -buffer, -subregion
|
||||
// [4] DTCM: 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, -cache, -buffer, -subregion
|
||||
nxp.MPU.SetRBAR(4, 0x20000000)
|
||||
nxp.MPU.SetRASR(nxp.RGNSZ_512KB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, false, false, false)
|
||||
|
||||
// [5] RAM (AXI):
|
||||
// 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion
|
||||
// [5] RAM (AXI): 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion
|
||||
nxp.MPU.SetRBAR(5, 0x20200000)
|
||||
nxp.MPU.SetRASR(nxp.RGNSZ_512KB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, true, true, false)
|
||||
|
||||
// [6] FlexSPI:
|
||||
// 512 MiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion
|
||||
// [6] FlexSPI: 512 MiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion
|
||||
nxp.MPU.SetRBAR(6, 0x70000000)
|
||||
nxp.MPU.SetRASR(nxp.RGNSZ_512MB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, true, true, false)
|
||||
|
||||
// [7] QSPI flash:
|
||||
// 2 MiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion
|
||||
// [7] QSPI flash: 2 MiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion
|
||||
nxp.MPU.SetRBAR(7, 0x60000000)
|
||||
nxp.MPU.SetRASR(nxp.RGNSZ_2MB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, true, true, false)
|
||||
|
||||
|
||||
@@ -12,14 +12,14 @@ import (
|
||||
|
||||
type timeUnit int64
|
||||
|
||||
const ( // HW divides 24 MHz XTALOSC down to 100 kHz
|
||||
const (
|
||||
lastCycle = SYSTICK_FREQ/1000 - 1
|
||||
cyclesPerMicro = CORE_FREQ / 1000000
|
||||
)
|
||||
|
||||
const (
|
||||
PIT_FREQ = PERCLK_FREQ
|
||||
pitCyclesPerMicro = PIT_FREQ / 1000000
|
||||
pitFreq = OSC_FREQ // PIT/GPT are muxed to 24 MHz OSC
|
||||
pitCyclesPerMicro = pitFreq / 1000000
|
||||
pitSleepTimer = 0 // x4 32-bit PIT timers [0..3]
|
||||
)
|
||||
|
||||
@@ -32,16 +32,11 @@ var (
|
||||
|
||||
var (
|
||||
// debug exception and monitor control
|
||||
DEMCR = (*volatile.Register32)(unsafe.Pointer(uintptr(0xe000edfc)))
|
||||
DWT_CTRL = (*volatile.Register32)(unsafe.Pointer(uintptr(0xe0001000)))
|
||||
DEM_CR = (*volatile.Register32)(unsafe.Pointer(uintptr(0xe000edfc)))
|
||||
DWT_CR = (*volatile.Register32)(unsafe.Pointer(uintptr(0xe0001000)))
|
||||
DWT_CYCCNT = (*volatile.Register32)(unsafe.Pointer(uintptr(0xe0001004)))
|
||||
)
|
||||
|
||||
const (
|
||||
DEMCR_TRCENA = 0x01000000 // enable debugging & monitoring blocks
|
||||
DWT_CTRL_CYCCNTENA = 0x00000001 // cycle count register
|
||||
)
|
||||
|
||||
func ticksToNanoseconds(ticks timeUnit) int64 {
|
||||
return int64(ticks) * 1000
|
||||
}
|
||||
@@ -51,22 +46,30 @@ func nanosecondsToTicks(ns int64) timeUnit {
|
||||
}
|
||||
|
||||
func initSysTick() {
|
||||
// disable if already running
|
||||
|
||||
const (
|
||||
traceEnable = 0x01000000 // enable debugging & monitoring blocks
|
||||
cycleCountEnable = 0x00000001 // cycle count register
|
||||
)
|
||||
|
||||
// disable SysTick if already running
|
||||
if arm.SYST.SYST_CSR.HasBits(arm.SYST_CSR_ENABLE_Msk) {
|
||||
arm.SYST.SYST_CSR.ClearBits(arm.SYST_CSR_ENABLE_Msk)
|
||||
}
|
||||
|
||||
// zeroize the counter
|
||||
tickCount.Set(0)
|
||||
arm.SYST.SYST_RVR.Set(lastCycle)
|
||||
arm.SYST.SYST_CVR.Set(0)
|
||||
arm.SYST.SYST_CSR.Set(arm.SYST_CSR_TICKINT | arm.SYST_CSR_ENABLE)
|
||||
|
||||
// set SysTick and PendSV priority to 32
|
||||
nxp.SystemControl.SHPR3.Set((0x20 << nxp.SCB_SHPR3_PRI_15_Pos) |
|
||||
(0x20 << nxp.SCB_SHPR3_PRI_14_Pos))
|
||||
|
||||
// turn on cycle counter
|
||||
DEMCR.SetBits(DEMCR_TRCENA)
|
||||
DWT_CTRL.SetBits(DWT_CTRL_CYCCNTENA)
|
||||
DEM_CR.SetBits(traceEnable)
|
||||
DWT_CR.SetBits(cycleCountEnable)
|
||||
cycleCount.Set(DWT_CYCCNT.Get())
|
||||
|
||||
// enable PIT, disable counters
|
||||
@@ -74,6 +77,7 @@ func initSysTick() {
|
||||
for i := range nxp.PIT.TIMER {
|
||||
nxp.PIT.TIMER[i].TCTRL.Set(0)
|
||||
}
|
||||
|
||||
// register sleep timer interrupt
|
||||
pitTimeout = interrupt.New(nxp.IRQ_PIT, timerWake)
|
||||
pitTimeout.SetPriority(0x21)
|
||||
@@ -101,7 +105,13 @@ func ticks() timeUnit {
|
||||
cycs := cycleCount.Get()
|
||||
curr := DWT_CYCCNT.Get()
|
||||
arm.EnableInterrupts(mask)
|
||||
frac := uint64((curr-cycs)*0xFFFFFFFF/cyclesPerMicro) >> 32
|
||||
var diff uint32
|
||||
if curr < cycs { // cycle counter overflow/rollover occurred
|
||||
diff = (0xFFFFFFFF - cycs) + curr
|
||||
} else {
|
||||
diff = curr - cycs
|
||||
}
|
||||
frac := uint64(diff*0xFFFFFFFF/cyclesPerMicro) >> 32
|
||||
if frac > 1000 {
|
||||
frac = 1000
|
||||
}
|
||||
@@ -111,15 +121,14 @@ func ticks() timeUnit {
|
||||
func sleepTicks(duration timeUnit) {
|
||||
if duration >= 0 {
|
||||
curr := ticks()
|
||||
last := curr + duration
|
||||
last := curr + duration // 64-bit overflow unlikely
|
||||
for curr < last {
|
||||
cycles := timeUnit((last - curr) / pitCyclesPerMicro)
|
||||
if cycles > 0xFFFFFFFF {
|
||||
cycles = 0xFFFFFFFF
|
||||
}
|
||||
if !timerSleep(uint32(cycles)) {
|
||||
// return early due to interrupt
|
||||
return
|
||||
return // return early due to interrupt
|
||||
}
|
||||
curr = ticks()
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user