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https://github.com/tinygo-org/tinygo.git
synced 2026-08-09 13:33:39 +00:00
teensy40: refactor to remove unnecessary code and constants
This commit is contained in:
ardnew
Ron Evans
@@ -11,75 +11,42 @@ import (
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"unsafe"
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)
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// Clock represents an individual peripheral clock that may be enabled/disabled
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// at runtime. Clocks also have a method `Mux` for selecting the clock source
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// and a method `Div` for selecting the hardware divisor. Note that many
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// peripherals have an independent prescalar configuration applied to the output
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// of this divisor.
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type (
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Clock uint32
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Gate uint8
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ClockMode uint8
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// PLL configuration for ARM
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ClockConfigArmPll struct {
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LoopDivider uint32 // PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*LoopDivider/2.
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Src uint8 // Pll clock source, reference _clock_pll_clk_src
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}
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// PLL configuration for System
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ClockConfigSysPll struct {
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LoopDivider uint8 // PLL loop divider. Intended to be 1 (528M): 0 - Fout=Fref*20, 1 - Fout=Fref*22
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Numerator uint32 // 30 bit Numerator of fractional loop divider.
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Denominator uint32 // 30 bit Denominator of fractional loop divider
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Src uint8 // Pll clock source, reference _clock_pll_clk_src
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SsStop uint16 // Stop value to get frequency change.
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SsEnable uint8 // Enable spread spectrum modulation
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SsStep uint16 // Step value to get frequency change step.
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}
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// PLL configuration for USB
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ClockConfigUsbPll struct {
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Instance uint8 // USB PLL number (1 or 2)
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LoopDivider uint8 // PLL loop divider: 0 - Fout=Fref*20, 1 - Fout=Fref*22
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Src uint8 // Pll clock source, reference _clock_pll_clk_src
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}
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// PLL configuration for AUDIO
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ClockConfigAudioPll struct {
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LoopDivider uint8 // PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.
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PostDivider uint8 // Divider after the PLL, should only be 1, 2, 4, 8, 16.
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Numerator uint32 // 30 bit Numerator of fractional loop divider.
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Denominator uint32 // 30 bit Denominator of fractional loop divider
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Src uint8 // Pll clock source, reference _clock_pll_clk_src
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}
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// PLL configuration for VIDEO
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ClockConfigVideoPll struct {
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LoopDivider uint8 // PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.
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PostDivider uint8 // Divider after the PLL, should only be 1, 2, 4, 8, 16.
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Numerator uint32 // 30 bit Numerator of fractional loop divider.
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Denominator uint32 // 30 bit Denominator of fractional loop divider
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Src uint8 // Pll clock source, reference _clock_pll_clk_src
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}
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// PLL configuration for ENET
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ClockConfigEnetPll struct {
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EnableClkOutput bool // Power on and enable PLL clock output for ENET0.
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EnableClkOutput25M bool // Power on and enable PLL clock output for ENET2.
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LoopDivider uint8 // Controls the frequency of the ENET0 reference clock: b00=25MHz, b01=50MHz, b10=100MHz (not 50% duty cycle), b11=125MHz
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Src uint8 // Pll clock source, reference _clock_pll_clk_src
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EnableClkOutput1 bool // Power on and enable PLL clock output for ENET1.
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LoopDivider1 uint8 // Controls the frequency of the ENET1 reference clock: b00 25MHz, b01 50MHz, b10 100MHz (not 50% duty cycle), b11 125MHz
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}
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)
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// Enable activates or deactivates the clock gate of receiver Clock c.
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func (c Clock) Enable(enable bool) {
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if enable {
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c.setGate(clockNeededRunWait)
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} else {
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c.setGate(clockNotNeeded)
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}
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}
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// Mux selects a clock source for the mux of the receiver Clock c.
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func (c Clock) Mux(mux uint32) { c.setCcm(mux) }
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// Div configures the prescalar divisor of the receiver Clock c.
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func (c Clock) Div(div uint32) { c.setCcm(div) }
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const (
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ModeClkRun ClockMode = 0 // Remain in run mode
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ModeClkWait ClockMode = 1 // Transfer to wait mode
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ModeClkStop ClockMode = 2 // Transfer to stop mode
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ClockModeRun ClockMode = 0 // Remain in run mode
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ClockModeWait ClockMode = 1 // Transfer to wait mode
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ClockModeStop ClockMode = 2 // Transfer to stop mode
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)
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const (
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GateClkNotNeeded Gate = 0 // Clock is off during all modes
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GateClkNeededRun Gate = 1 // Clock is on in run mode, but off in WAIT and STOP modes
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GateClkNeededRunWait Gate = 3 // Clock is on during all modes, except STOP mode
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)
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// Set configures the run mode of the MCU.
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func (m ClockMode) Set() {
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CCM.CLPCR.Set((CCM.CLPCR.Get() & ^uint32(CCM_CLPCR_LPM_Msk)) |
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((uint32(m) << CCM_CLPCR_LPM_Pos) & CCM_CLPCR_LPM_Msk))
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}
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// Named oscillators
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const (
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@@ -259,6 +226,7 @@ const (
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ClockPfd3 Clock = 3 // PLL PFD3
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)
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// Named clock muxes of integrated peripherals
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const (
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MuxIpPll3Sw Clock = (offCCSR & 0xFF) | (CCM_CCSR_PLL3_SW_CLK_SEL_Pos << 8) | (((CCM_CCSR_PLL3_SW_CLK_SEL_Msk >> CCM_CCSR_PLL3_SW_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // pll3_sw_clk mux name
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MuxIpPeriph Clock = (offCBCDR & 0xFF) | (CCM_CBCDR_PERIPH_CLK_SEL_Pos << 8) | (((CCM_CBCDR_PERIPH_CLK_SEL_Msk >> CCM_CBCDR_PERIPH_CLK_SEL_Pos) & 0x1FFF) << 13) | (CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_Pos << 26) // periph mux name
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@@ -286,6 +254,7 @@ const (
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MuxIpCsi Clock = (offCSCDR3 & 0xFF) | (CCM_CSCDR3_CSI_CLK_SEL_Pos << 8) | (((CCM_CSCDR3_CSI_CLK_SEL_Msk >> CCM_CSCDR3_CSI_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // csi mux name
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)
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// Named hardware clock divisors of integrated peripherals
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const (
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DivIpArm Clock = (offCACRR & 0xFF) | (CCM_CACRR_ARM_PODF_Pos << 8) | (((CCM_CACRR_ARM_PODF_Msk >> CCM_CACRR_ARM_PODF_Pos) & 0x1FFF) << 13) | (CCM_CDHIPR_ARM_PODF_BUSY_Pos << 26) // core div name
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DivIpPeriphClk2 Clock = (offCBCDR & 0xFF) | (CCM_CBCDR_PERIPH_CLK2_PODF_Pos << 8) | (((CCM_CBCDR_PERIPH_CLK2_PODF_Msk >> CCM_CBCDR_PERIPH_CLK2_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // periph clock2 div name
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@@ -345,7 +314,7 @@ const (
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noBusyWait = 0x20
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)
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// analog pll definition
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// analog PLL definition
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const (
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pllBypassPos = 16
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pllBypassClkSrcMsk = 0xC000
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@@ -358,29 +327,14 @@ const (
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pllSrcClkPN = 1 // Pll clock source CLK1_P and CLK1_N
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)
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// Set configures the run mode of the MCU.
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func (m ClockMode) Set() {
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CCM.CLPCR.Set((CCM.CLPCR.Get() & ^uint32(CCM_CLPCR_LPM_Msk)) |
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((uint32(m) << CCM_CLPCR_LPM_Pos) & CCM_CLPCR_LPM_Msk))
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}
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const (
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clockNotNeeded uint32 = 0 // Clock is off during all modes
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clockNeededRun uint32 = 1 // Clock is on in run mode, but off in WAIT and STOP modes
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clockNeededRunWait uint32 = 3 // Clock is on during all modes, except STOP mode
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)
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// Enable activates or deactivates the clock gate of receiver Clock clk.
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func (clk Clock) Enable(enable bool) {
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if enable {
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clk.control(GateClkNeededRunWait)
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} else {
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clk.control(GateClkNotNeeded)
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}
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}
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// Mux selects a clock source for the mux of the receiver Clock clk.
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func (clk Clock) Mux(mux uint32) { clk.ccm(mux) }
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// Div configures the prescalar divisor of the receiver Clock clk.
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func (clk Clock) Div(div uint32) { clk.ccm(div) }
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// getCCGR returns the CCM clock gating register for the receiver clk.
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func (clk Clock) getCCGR() *volatile.Register32 {
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// getGate returns the CCM clock gating register for the receiver clk.
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func (clk Clock) getGate() *volatile.Register32 {
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switch clk >> 8 {
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case 0:
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return &CCM.CCGR0
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@@ -403,14 +357,14 @@ func (clk Clock) getCCGR() *volatile.Register32 {
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}
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}
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// control enables or disables the receiver clk using its gating register.
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func (clk Clock) control(value Gate) {
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reg := clk.getCCGR()
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// setGate enables or disables the receiver clk using its gating register.
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func (clk Clock) setGate(value uint32) {
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reg := clk.getGate()
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shift := clk & 0x1F
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reg.Set((reg.Get() & ^(3 << shift)) | (uint32(value) << shift))
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reg.Set((reg.Get() & ^(3 << shift)) | (value << shift))
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}
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func (clk Clock) ccm(value uint32) {
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func (clk Clock) setCcm(value uint32) {
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const ccmBase = 0x400fc000
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reg := (*volatile.Register32)(unsafe.Pointer(uintptr(ccmBase + (uint32(clk) & 0xFF))))
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msk := ((uint32(clk) >> 13) & 0x1FFF) << ((uint32(clk) >> 8) & 0x1F)
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@@ -423,260 +377,6 @@ func (clk Clock) ccm(value uint32) {
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}
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}
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// GetFreq returns the calculated frequency of the receiver clock clk.
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func (clk Clock) GetFreq() uint32 {
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switch clk {
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case ClockCpu, ClockAhb:
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return getAhbFreq()
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case ClockSemc:
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return getSemcFreq()
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case ClockIpg:
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return getIpgFreq()
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case ClockPer:
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return getPerClkFreq()
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case ClockOsc:
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return getOscFreq()
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case ClockRtc:
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return getRtcFreq()
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case ClockArmPll:
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return ClockPllArm.getPllFreq()
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case ClockUsb1Pll:
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return ClockPllUsb1.getPllFreq()
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case ClockUsb1PllPfd0:
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return ClockPfd0.getUsb1PfdFreq()
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case ClockUsb1PllPfd1:
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return ClockPfd1.getUsb1PfdFreq()
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case ClockUsb1PllPfd2:
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return ClockPfd2.getUsb1PfdFreq()
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case ClockUsb1PllPfd3:
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return ClockPfd3.getUsb1PfdFreq()
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case ClockUsb2Pll:
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return ClockPllUsb2.getPllFreq()
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case ClockSysPll:
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return ClockPllSys.getPllFreq()
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case ClockSysPllPfd0:
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return ClockPfd0.getSysPfdFreq()
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case ClockSysPllPfd1:
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return ClockPfd1.getSysPfdFreq()
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case ClockSysPllPfd2:
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return ClockPfd2.getSysPfdFreq()
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case ClockSysPllPfd3:
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return ClockPfd3.getSysPfdFreq()
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case ClockEnetPll0:
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return ClockPllEnet.getPllFreq()
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case ClockEnetPll1:
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return ClockPllEnet2.getPllFreq()
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case ClockEnetPll2:
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return ClockPllEnet25M.getPllFreq()
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case ClockAudioPll:
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return ClockPllAudio.getPllFreq()
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case ClockVideoPll:
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return ClockPllVideo.getPllFreq()
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default:
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panic("nxp: invalid clock")
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}
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}
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// getOscFreq returns the XTAL OSC clock frequency
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func getOscFreq() uint32 {
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return 24000000 // 24 MHz
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}
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// getRtcFreq returns the RTC clock frequency
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func getRtcFreq() uint32 {
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return 32768 // 32.768 kHz
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}
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func ccmCbcmrPeriphClk2Sel(n uint32) uint32 {
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return (n << CCM_CBCMR_PERIPH_CLK2_SEL_Pos) & CCM_CBCMR_PERIPH_CLK2_SEL_Msk
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}
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func ccmCbcmrPrePeriphClkSel(n uint32) uint32 {
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return (n << CCM_CBCMR_PRE_PERIPH_CLK_SEL_Pos) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_Msk
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}
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// getPeriphClkFreq returns the PERIPH clock frequency
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func getPeriphClkFreq() uint32 {
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freq := uint32(0)
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if CCM.CBCDR.HasBits(CCM_CBCDR_PERIPH_CLK_SEL_Msk) {
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// Periph_clk2_clk -> Periph_clk
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switch CCM.CBCMR.Get() & CCM_CBCMR_PERIPH_CLK2_SEL_Msk {
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case ccmCbcmrPeriphClk2Sel(0):
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// Pll3_sw_clk -> Periph_clk2_clk -> Periph_clk
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freq = ClockPllUsb1.getPllFreq()
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case ccmCbcmrPeriphClk2Sel(1):
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// Osc_clk -> Periph_clk2_clk -> Periph_clk
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freq = getOscFreq()
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case ccmCbcmrPeriphClk2Sel(2):
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freq = ClockPllSys.getPllFreq()
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case ccmCbcmrPeriphClk2Sel(3):
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freq = 0
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}
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freq /= ((CCM.CBCDR.Get() & CCM_CBCDR_PERIPH_CLK2_PODF_Msk) >> CCM_CBCDR_PERIPH_CLK2_PODF_Pos) + 1
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} else {
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// Pre_Periph_clk -> Periph_clk
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switch CCM.CBCMR.Get() & CCM_CBCMR_PRE_PERIPH_CLK_SEL_Msk {
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case ccmCbcmrPrePeriphClkSel(0):
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// PLL2 -> Pre_Periph_clk -> Periph_clk
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freq = ClockPllSys.getPllFreq()
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case ccmCbcmrPrePeriphClkSel(1):
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// PLL2 PFD2 -> Pre_Periph_clk -> Periph_clk
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freq = ClockPfd2.getSysPfdFreq()
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case ccmCbcmrPrePeriphClkSel(2):
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// PLL2 PFD0 -> Pre_Periph_clk -> Periph_clk
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freq = ClockPfd0.getSysPfdFreq()
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case ccmCbcmrPrePeriphClkSel(3):
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// PLL1 divided(/2) -> Pre_Periph_clk -> Periph_clk
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freq = ClockPllArm.getPllFreq() / (((CCM.CACRR.Get() & CCM_CACRR_ARM_PODF_Msk) >> CCM_CACRR_ARM_PODF_Pos) + 1)
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}
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}
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return freq
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}
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// getAhbFreq returns the AHB clock frequency
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func getAhbFreq() uint32 {
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return getPeriphClkFreq() / (((CCM.CBCDR.Get() & CCM_CBCDR_AHB_PODF_Msk) >> CCM_CBCDR_AHB_PODF_Pos) + 1)
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}
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// getSemcFreq returns the SEMC clock frequency
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func getSemcFreq() uint32 {
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freq := uint32(0)
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if CCM.CBCDR.HasBits(CCM_CBCDR_SEMC_CLK_SEL_Msk) {
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// SEMC alternative clock -> SEMC Clock
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if CCM.CBCDR.HasBits(CCM_CBCDR_SEMC_ALT_CLK_SEL_Msk) {
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// PLL3 PFD1 -> SEMC alternative clock -> SEMC Clock
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freq = ClockPfd1.getUsb1PfdFreq()
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} else {
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// PLL2 PFD2 -> SEMC alternative clock -> SEMC Clock
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freq = ClockPfd2.getSysPfdFreq()
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}
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} else {
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// Periph_clk -> SEMC Clock
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freq = getPeriphClkFreq()
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}
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freq /= ((CCM.CBCDR.Get() & CCM_CBCDR_SEMC_PODF_Msk) >> CCM_CBCDR_SEMC_PODF_Pos) + 1
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return freq
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}
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// getIpgFreq returns the IPG clock frequency
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func getIpgFreq() uint32 {
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return getAhbFreq() / (((CCM.CBCDR.Get() & CCM_CBCDR_IPG_PODF_Msk) >> CCM_CBCDR_IPG_PODF_Pos) + 1)
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}
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// getPerClkFreq returns the PER clock frequency
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func getPerClkFreq() uint32 {
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freq := uint32(0)
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if CCM.CSCMR1.HasBits(CCM_CSCMR1_PERCLK_CLK_SEL_Msk) {
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// Osc_clk -> PER Cloc
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freq = getOscFreq()
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} else {
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// Periph_clk -> AHB Clock -> IPG Clock -> PER Clock
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freq = getIpgFreq()
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}
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return freq/((CCM.CSCMR1.Get()&CCM_CSCMR1_PERCLK_PODF_Msk)>>
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CCM_CSCMR1_PERCLK_PODF_Pos) + 1
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}
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// getPllFreq returns the clock frequency of the receiver (PLL) clock clk
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func (clk Clock) getPllFreq() uint32 {
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enetRefClkFreq := []uint32{
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25000000, // 25 MHz
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50000000, // 50 MHz
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100000000, // 100 MHz
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125000000, // 125 MHz
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}
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// check if PLL is enabled
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if !clk.isPllEnabled() {
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return 0
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}
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// get pll reference clock
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freq := clk.getBypassFreq()
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// check if pll is bypassed
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if clk.isPllBypassed() {
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return freq
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}
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switch clk {
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case ClockPllArm:
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freq *= (CCM_ANALOG.PLL_ARM.Get() & CCM_ANALOG_PLL_ARM_DIV_SELECT_Msk) >> CCM_ANALOG_PLL_ARM_DIV_SELECT_Pos
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freq >>= 1
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case ClockPllSys:
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// PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM).
|
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fFreq := float64(freq) * float64(CCM_ANALOG.PLL_SYS_NUM.Get())
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fFreq /= float64(CCM_ANALOG.PLL_SYS_DENOM.Get())
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if CCM_ANALOG.PLL_SYS.HasBits(CCM_ANALOG_PLL_SYS_DIV_SELECT_Msk) {
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freq *= 22
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} else {
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freq *= 20
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}
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freq += uint32(fFreq)
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||||
case ClockPllUsb1:
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if CCM_ANALOG.PLL_USB1.HasBits(CCM_ANALOG_PLL_USB1_DIV_SELECT_Msk) {
|
||||
freq *= 22
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} else {
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freq *= 20
|
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}
|
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case ClockPllEnet:
|
||||
divSelect := (CCM_ANALOG.PLL_ENET.Get() & CCM_ANALOG_PLL_ENET_DIV_SELECT_Msk) >> CCM_ANALOG_PLL_ENET_DIV_SELECT_Pos
|
||||
freq = enetRefClkFreq[divSelect]
|
||||
case ClockPllEnet2:
|
||||
divSelect := (CCM_ANALOG.PLL_ENET.Get() & CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_Msk) >> CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_Pos
|
||||
freq = enetRefClkFreq[divSelect]
|
||||
case ClockPllEnet25M:
|
||||
// ref_enetpll1 if fixed at 25MHz.
|
||||
freq = 25000000
|
||||
case ClockPllUsb2:
|
||||
if CCM_ANALOG.PLL_USB2.HasBits(CCM_ANALOG_PLL_USB2_DIV_SELECT_Msk) {
|
||||
freq *= 22
|
||||
} else {
|
||||
freq *= 20
|
||||
}
|
||||
default:
|
||||
freq = 0
|
||||
}
|
||||
return freq
|
||||
}
|
||||
|
||||
// getSysPfdFreq returns current system PLL PFD output frequency
|
||||
func (clk Clock) getSysPfdFreq() uint32 {
|
||||
freq := ClockPllSys.getPllFreq()
|
||||
switch clk {
|
||||
case ClockPfd0:
|
||||
freq /= (CCM_ANALOG.PFD_528.Get() & CCM_ANALOG_PFD_528_PFD0_FRAC_Msk) >> CCM_ANALOG_PFD_528_PFD0_FRAC_Pos
|
||||
case ClockPfd1:
|
||||
freq /= (CCM_ANALOG.PFD_528.Get() & CCM_ANALOG_PFD_528_PFD1_FRAC_Msk) >> CCM_ANALOG_PFD_528_PFD1_FRAC_Pos
|
||||
case ClockPfd2:
|
||||
freq /= (CCM_ANALOG.PFD_528.Get() & CCM_ANALOG_PFD_528_PFD2_FRAC_Msk) >> CCM_ANALOG_PFD_528_PFD2_FRAC_Pos
|
||||
case ClockPfd3:
|
||||
freq /= (CCM_ANALOG.PFD_528.Get() & CCM_ANALOG_PFD_528_PFD3_FRAC_Msk) >> CCM_ANALOG_PFD_528_PFD3_FRAC_Pos
|
||||
default:
|
||||
freq = 0
|
||||
}
|
||||
return freq * 18
|
||||
}
|
||||
|
||||
// getUsb1PfdFreq returns current USB1 PLL PFD output frequency
|
||||
func (clk Clock) getUsb1PfdFreq() uint32 {
|
||||
freq := ClockPllUsb1.getPllFreq()
|
||||
switch clk {
|
||||
case ClockPfd0:
|
||||
freq /= (CCM_ANALOG.PFD_480.Get() & CCM_ANALOG_PFD_480_PFD0_FRAC_Msk) >> CCM_ANALOG_PFD_480_PFD0_FRAC_Pos
|
||||
case ClockPfd1:
|
||||
freq /= (CCM_ANALOG.PFD_480.Get() & CCM_ANALOG_PFD_480_PFD1_FRAC_Msk) >> CCM_ANALOG_PFD_480_PFD1_FRAC_Pos
|
||||
case ClockPfd2:
|
||||
freq /= (CCM_ANALOG.PFD_480.Get() & CCM_ANALOG_PFD_480_PFD2_FRAC_Msk) >> CCM_ANALOG_PFD_480_PFD2_FRAC_Pos
|
||||
case ClockPfd3:
|
||||
freq /= (CCM_ANALOG.PFD_480.Get() & CCM_ANALOG_PFD_480_PFD3_FRAC_Msk) >> CCM_ANALOG_PFD_480_PFD3_FRAC_Pos
|
||||
default:
|
||||
freq = 0
|
||||
}
|
||||
return freq * 18
|
||||
}
|
||||
|
||||
func setSysPfd(value ...uint32) {
|
||||
for i, val := range value {
|
||||
pfd528 := CCM_ANALOG.PFD_528.Get() &
|
||||
@@ -701,40 +401,10 @@ func setUsb1Pfd(value ...uint32) {
|
||||
}
|
||||
}
|
||||
|
||||
func (clk Clock) isPllEnabled() bool {
|
||||
const ccmAnalogBase = 0x400d8000
|
||||
addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF)
|
||||
pos := uint32(1 << (uint32(clk) & 0x1F))
|
||||
return ((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).HasBits(pos)
|
||||
}
|
||||
|
||||
func (clk Clock) isPllBypassed() bool {
|
||||
const ccmAnalogBase = 0x400d8000
|
||||
addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF)
|
||||
pos := uint32(1 << pllBypassPos)
|
||||
return ((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).HasBits(pos)
|
||||
}
|
||||
|
||||
func (clk Clock) getBypassFreq() uint32 {
|
||||
const ccmAnalogBase = 0x400d8000
|
||||
addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF)
|
||||
src := (((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).Get() &
|
||||
pllBypassClkSrcMsk) >> pllBypassClkSrcPos
|
||||
if src == uint32(pllSrc24M) {
|
||||
return getOscFreq()
|
||||
}
|
||||
return 0
|
||||
}
|
||||
|
||||
func (clk Clock) bypass(bypass bool) {
|
||||
const ccmAnalogBase = 0x400d8000
|
||||
if bypass {
|
||||
addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF) + 4
|
||||
((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).Set(1 << pllBypassPos)
|
||||
} else {
|
||||
addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF) + 8
|
||||
((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).Set(1 << pllBypassPos)
|
||||
}
|
||||
// PLL configuration for ARM
|
||||
type ClockConfigArmPll struct {
|
||||
LoopDivider uint32 // PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*LoopDivider/2.
|
||||
Src uint8 // Pll clock source, reference _clock_pll_clk_src
|
||||
}
|
||||
|
||||
func (cfg ClockConfigArmPll) Configure() {
|
||||
@@ -757,6 +427,17 @@ func (cfg ClockConfigArmPll) Configure() {
|
||||
CCM_ANALOG.PLL_ARM.ClearBits(CCM_ANALOG_PLL_ARM_BYPASS_Msk)
|
||||
}
|
||||
|
||||
// PLL configuration for System
|
||||
type ClockConfigSysPll struct {
|
||||
LoopDivider uint8 // PLL loop divider. Intended to be 1 (528M): 0 - Fout=Fref*20, 1 - Fout=Fref*22
|
||||
Numerator uint32 // 30 bit Numerator of fractional loop divider.
|
||||
Denominator uint32 // 30 bit Denominator of fractional loop divider
|
||||
Src uint8 // Pll clock source, reference _clock_pll_clk_src
|
||||
SsStop uint16 // Stop value to get frequency change.
|
||||
SsEnable uint8 // Enable spread spectrum modulation
|
||||
SsStep uint16 // Step value to get frequency change step.
|
||||
}
|
||||
|
||||
func (cfg ClockConfigSysPll) Configure(pfd ...uint32) {
|
||||
|
||||
// bypass PLL first
|
||||
@@ -790,6 +471,13 @@ func (cfg ClockConfigSysPll) Configure(pfd ...uint32) {
|
||||
setSysPfd(pfd...)
|
||||
}
|
||||
|
||||
// PLL configuration for USB
|
||||
type ClockConfigUsbPll struct {
|
||||
Instance uint8 // USB PLL number (1 or 2)
|
||||
LoopDivider uint8 // PLL loop divider: 0 - Fout=Fref*20, 1 - Fout=Fref*22
|
||||
Src uint8 // Pll clock source, reference _clock_pll_clk_src
|
||||
}
|
||||
|
||||
func (cfg ClockConfigUsbPll) Configure(pfd ...uint32) {
|
||||
|
||||
switch cfg.Instance {
|
||||
@@ -34,16 +34,6 @@ type (
|
||||
Extension uint32
|
||||
)
|
||||
|
||||
// MPU Type Register Definitions
|
||||
const (
|
||||
MPU_TYPE_IREGION_Pos = 16 // MPU TYPE: IREGION Position
|
||||
MPU_TYPE_IREGION_Msk = 0xFF << MPU_TYPE_IREGION_Pos // MPU TYPE: IREGION Mask
|
||||
MPU_TYPE_DREGION_Pos = 8 // MPU TYPE: DREGION Position
|
||||
MPU_TYPE_DREGION_Msk = 0xFF << MPU_TYPE_DREGION_Pos // MPU TYPE: DREGION Mask
|
||||
MPU_TYPE_SEPARATE_Pos = 0 // MPU TYPE: SEPARATE Position
|
||||
MPU_TYPE_SEPARATE_Msk = 1 // MPU TYPE: SEPARATE Mask
|
||||
)
|
||||
|
||||
// MPU Control Register Definitions
|
||||
const (
|
||||
MPU_CTRL_PRIVDEFENA_Pos = 2 // MPU CTRL: PRIVDEFENA Position
|
||||
@@ -54,12 +44,6 @@ const (
|
||||
MPU_CTRL_ENABLE_Msk = 1 // MPU CTRL: ENABLE Mask
|
||||
)
|
||||
|
||||
// MPU Region Number Register Definitions
|
||||
const (
|
||||
MPU_RNR_REGION_Pos = 0 // MPU RNR: REGION Position
|
||||
MPU_RNR_REGION_Msk = 0xFF // MPU RNR: REGION Mask
|
||||
)
|
||||
|
||||
// MPU Region Base Address Register Definitions
|
||||
const (
|
||||
MPU_RBAR_ADDR_Pos = 5 // MPU RBAR: ADDR Position
|
||||
@@ -161,11 +145,11 @@ func (mpu *MPU_Type) Enable(enable bool) {
|
||||
dsb 0xF
|
||||
isb 0xF
|
||||
`, nil)
|
||||
EnableDcache(true)
|
||||
EnableIcache(true)
|
||||
enableDcache(true)
|
||||
enableIcache(true)
|
||||
} else {
|
||||
EnableIcache(false)
|
||||
EnableDcache(false)
|
||||
enableIcache(false)
|
||||
enableDcache(false)
|
||||
arm.AsmFull(`
|
||||
dmb 0xF
|
||||
`, nil)
|
||||
@@ -200,7 +184,7 @@ func (mpu *MPU_Type) SetRASR(size RegionSize, access AccessPerms, ext Extension,
|
||||
MPU_RASR_ENABLE_Msk)
|
||||
}
|
||||
|
||||
func EnableIcache(enable bool) {
|
||||
func enableIcache(enable bool) {
|
||||
if enable != SystemControl.CCR.HasBits(SCB_CCR_IC_Msk) {
|
||||
if enable {
|
||||
arm.AsmFull(`
|
||||
@@ -232,7 +216,7 @@ func EnableIcache(enable bool) {
|
||||
}
|
||||
}
|
||||
|
||||
func EnableDcache(enable bool) {
|
||||
func enableDcache(enable bool) {
|
||||
if enable != SystemControl.CCR.HasBits(SCB_CCR_DC_Msk) {
|
||||
if enable {
|
||||
SystemControl.CSSELR.Set(0)
|
||||
Reference in New Issue
Block a user