stm32: use stm32-rs SVDs which are of much higher quality

This commit changes the number of wait states for the stm32f103 chip to
2 instead of 4. This gets it back in line with the datasheet, but it
also has the side effect of breaking I2C. Therefore, another (seemingly
unrelated) change is needed: the i2cTimeout constant must be increased
to a higher value to adjust to the lower flash wait states - presumably
because the lower number of wait states allows the chip to run code
faster.

src/device/stm32/stm32-moder-bitfields.go

@@ -1,57 +0,0 @@
-// Hand created file. DO NOT DELETE.
-// STM32FXXX (except stm32f1xx) bitfield definitions that are not
-//  auto-generated by gen-device-svd.go
-
-// These apply to the stm32 families that use the MODER, OTYPE amd PUPDR
-//  registers for managing GPIO functionality.
-
-// Add in other families that use the same settings, e.g. stm32f0xx, etc
-
-// +build stm32,!stm32f103xx
-
-package stm32
-
-// AltFunc represents the alternate function peripherals that can be mapped to
-// the GPIO ports. Since these differ by what is supported on the stm32 family
-// they are defined in the more specific files
-type AltFunc uint8
-
-// Family-wide common post-reset AltFunc. This represents
-//  normal GPIO operation of the pins
-const AF0_SYSTEM AltFunc = 0
-
-const (
-	// Register values for the chip
-	// GPIOx_MODER
-	GPIOModeInput         = 0
-	GPIOModeOutputGeneral = 1
-	GPIOModeOutputAltFunc = 2
-	GPIOModeAnalog        = 3
-
-	// GPIOx_OTYPER
-	GPIOOutputTypePushPull  = 0
-	GPIOOutputTypeOpenDrain = 1
-
-	// GPIOx_OSPEEDR
-	GPIOSpeedLow      = 0
-	GPIOSpeedMid      = 1
-	GPIOSpeedHigh     = 2 // Note: this is also low speed on stm32f0, see RM0091
-	GPIOSpeedVeryHigh = 3
-
-	// GPIOx_PUPDR
-	GPIOPUPDRFloating = 0
-	GPIOPUPDRPullUp   = 1
-	GPIOPUPDRPullDown = 2
-)
-
-// SPI prescaler values fPCLK / X
-const (
-	SPI_PCLK_2   = 0
-	SPI_PCLK_4   = 1
-	SPI_PCLK_8   = 2
-	SPI_PCLK_16  = 3
-	SPI_PCLK_32  = 4
-	SPI_PCLK_64  = 5
-	SPI_PCLK_128 = 6
-	SPI_PCLK_256 = 7
-)

src/device/stm32/stm32f103xx-bitfields.go

@@ -1,88 +0,0 @@
-// Hand created file. DO NOT DELETE.
-// STM32F103XX bitfield definitions that are not auto-generated by gen-device-svd.go
-
-// +build stm32,stm32f103xx
-
-package stm32
-
-const (
-	// Flash Access Control Register flag values.
-	FLASH_ACR_LATENCY_0 = 0x00000001
-	FLASH_ACR_LATENCY_1 = 0x00000002
-	FLASH_ACR_LATENCY_2 = 0x00000004
-
-	// Reset and Clock Control Control Register flag values.
-
-	// System Clock source
-	RCC_CFGR_SW_HSI = 0
-	RCC_CFGR_SW_HSE = 1
-	RCC_CFGR_SW_PLL = 2
-
-	// Flags for when System Clock source is set.
-	RCC_CFGR_SWS_HSI = 0x00000000
-	RCC_CFGR_SWS_HSE = 0x00000004
-	RCC_CFGR_SWS_PLL = 0x00000008
-
-	// Sets PCLK1
-	RCC_CFGR_PPRE1_DIV_NONE = 0x00000000
-	RCC_CFGR_PPRE1_DIV_2    = 0x00000400
-	RCC_CFGR_PPRE1_DIV_4    = 0x00000500
-	RCC_CFGR_PPRE1_DIV_8    = 0x00000600
-	RCC_CFGR_PPRE1_DIV_16   = 0x00000700
-
-	// Sets PCLK2
-	RCC_CFGR_PPRE2_DIV_NONE = 0x00000000
-	RCC_CFGR_PPRE2_DIV_2    = 0x00002000
-	RCC_CFGR_PPRE2_DIV_4    = 0x00002800
-	RCC_CFGR_PPRE2_DIV_8    = 0x00003000
-	RCC_CFGR_PPRE2_DIV_16   = 0x00003800
-
-	// Sets PLL multiplier
-	RCC_CFGR_PLLMUL_2  = 0x00000000
-	RCC_CFGR_PLLMUL_3  = 0x00040000
-	RCC_CFGR_PLLMUL_4  = 0x00080000
-	RCC_CFGR_PLLMUL_5  = 0x000C0000
-	RCC_CFGR_PLLMUL_6  = 0x00100000
-	RCC_CFGR_PLLMUL_7  = 0x00140000
-	RCC_CFGR_PLLMUL_8  = 0x00180000
-	RCC_CFGR_PLLMUL_9  = 0x001C0000
-	RCC_CFGR_PLLMUL_10 = 0x00200000
-	RCC_CFGR_PLLMUL_11 = 0x00240000
-	RCC_CFGR_PLLMUL_12 = 0x00280000
-	RCC_CFGR_PLLMUL_13 = 0x002C0000
-	RCC_CFGR_PLLMUL_14 = 0x00300000
-	RCC_CFGR_PLLMUL_15 = 0x00340000
-	RCC_CFGR_PLLMUL_16 = 0x00380000
-
-	// RTC clock source
-	RCC_RTCCLKSource_LSE        = 0x00000100
-	RCC_RTCCLKSource_LSI        = 0x00000200
-	RCC_RTCCLKSource_HSE_Div128 = 0x00000300
-
-	// SPI settings
-	SPI_FirstBit_MSB = 0x0000
-	SPI_FirstBit_LSB = 0x0080
-
-	SPI_BaudRatePrescaler_2   = 0x0000
-	SPI_BaudRatePrescaler_4   = 0x0008
-	SPI_BaudRatePrescaler_8   = 0x0010
-	SPI_BaudRatePrescaler_16  = 0x0018
-	SPI_BaudRatePrescaler_32  = 0x0020
-	SPI_BaudRatePrescaler_64  = 0x0028
-	SPI_BaudRatePrescaler_128 = 0x0030
-	SPI_BaudRatePrescaler_256 = 0x0038
-
-	SPI_Direction_2Lines_FullDuplex = 0x0000
-	SPI_Direction_2Lines_RxOnly     = 0x0400
-	SPI_Direction_1Line_Rx          = 0x8000
-	SPI_Direction_1Line_Tx          = 0xC000
-
-	SPI_Mode_Master = 0x0104
-	SPI_Mode_Slave  = 0x0000
-
-	SPI_NSS_Soft = 0x0200
-	SPI_NSS_Hard = 0x0000
-
-	SPI_NSSInternalSoft_Set   = 0x0100
-	SPI_NSSInternalSoft_Reset = 0xFEFF
-)

src/device/stm32/stm32f4-altfunc-bitfields.go

@@ -1,28 +0,0 @@
-// Hand created file. DO NOT DELETE.
-// STM32FXXX (except stm32f1xx) bitfield definitions that are not
-//  auto-generated by gen-device-svd.go
-// +build stm32f4
-
-// Alternate function settings on the stm32f4 series
-
-package stm32
-
-const (
-	// Alternative peripheral pin functions
-	// AF0_SYSTEM is defined im the common bitfields package
-	AF1_TIM1_2                AltFunc = 1
-	AF2_TIM3_4_5                      = 2
-	AF3_TIM8_9_10_11                  = 3
-	AF4_I2C1_2_3                      = 4
-	AF5_SPI1_SPI2                     = 5
-	AF6_SPI3                          = 6
-	AF7_USART1_2_3                    = 7
-	AF8_USART4_5_6                    = 8
-	AF9_CAN1_CAN2_TIM12_13_14         = 9
-	AF10_OTG_FS_OTG_HS                = 10
-	AF11_ETH                          = 11
-	AF12_FSMC_SDIO_OTG_HS_1           = 12
-	AF13_DCMI                         = 13
-	AF14                              = 14
-	AF15_EVENTOUT                     = 15
-)