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stm32: add support for the STM32F4Discovery
Signed-off-by: Yusuke Mitsuki <mickey.happygolucky@gmail.com>
This commit is contained in:
Yusuke Mitsuki
committed by
Ayke van Laethem
Ayke van Laethem
parent
315cd4059f
commit
1322f404a6
@@ -0,0 +1,208 @@
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// +build stm32,stm32f407
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package runtime
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import (
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"device/arm"
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"device/stm32"
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"machine"
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)
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func init() {
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initCLK()
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initTIM3()
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machine.UART0.Configure(machine.UARTConfig{})
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initTIM7()
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}
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func putchar(c byte) {
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machine.UART0.WriteByte(c)
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}
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const (
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HSE_STARTUP_TIMEOUT = 0x0500
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/* PLL Options - See RM0090 Reference Manual pg. 95 */
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PLL_M = 8 /* PLL_VCO = (HSE_VALUE or HSI_VLAUE / PLL_M) * PLL_N */
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PLL_N = 336
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PLL_P = 2 /* SYSCLK = PLL_VCO / PLL_P */
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PLL_Q = 7 /* USB OTS FS, SDIO and RNG Clock = PLL_VCO / PLL_Q */
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)
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/*
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clock settings
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+-------------+--------+
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| HSE | 8mhz |
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| SYSCLK | 168mhz |
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| HCLK | 168mhz |
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| APB2(PCLK2) | 84mhz |
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| APB1(PCLK1) | 42mhz |
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+-------------+--------+
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*/
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func initCLK() {
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// Reset clock registers
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// Set HSION
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stm32.RCC.CR |= stm32.RCC_CR_HSION
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for (stm32.RCC.CR & stm32.RCC_CR_HSIRDY) == 0 {
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}
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// Reset CFGR
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stm32.RCC.CFGR = 0x00000000
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// Reset HSEON, CSSON and PLLON
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stm32.RCC.CR &= 0xFEF6FFFF
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// Reset PLLCFGR
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stm32.RCC.PLLCFGR = 0x24003010
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// Reset HSEBYP
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stm32.RCC.CR &= 0xFFFBFFFF
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// Disable all interrupts
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stm32.RCC.CIR = 0x00000000
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// Set up the clock
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var startupCounter uint32 = 0
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// Enable HSE
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stm32.RCC.CR = stm32.RCC_CR_HSEON
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// Wait till HSE is ready and if timeout is reached exit
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for {
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startupCounter++
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if (stm32.RCC.CR&stm32.RCC_CR_HSERDY != 0) || (startupCounter == HSE_STARTUP_TIMEOUT) {
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break
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}
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}
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if (stm32.RCC.CR & stm32.RCC_CR_HSERDY) != 0 {
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// Enable high performance mode, System frequency up to 168MHz
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stm32.RCC.APB1ENR |= stm32.RCC_APB1ENR_PWREN
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stm32.PWR.CR |= 0x4000 // PWR_CR_VOS
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// HCLK = SYSCLK / 1
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stm32.RCC.CFGR |= (0x0 << stm32.RCC_CFGR_HPRE_Pos)
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// PCLK2 = HCLK / 2
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stm32.RCC.CFGR |= (0x4 << stm32.RCC_CFGR_PPRE2_Pos)
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// PCLK1 = HCLK / 4
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stm32.RCC.CFGR |= (0x5 << stm32.RCC_CFGR_PPRE1_Pos)
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// Configure the main PLL
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// PLL Options - See RM0090 Reference Manual pg. 95
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stm32.RCC.PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) - 1) << 16) |
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(1 << stm32.RCC_PLLCFGR_PLLSRC_Pos) | (PLL_Q << 24)
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// Enable main PLL
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stm32.RCC.CR |= stm32.RCC_CR_PLLON
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// Wait till the main PLL is ready
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for (stm32.RCC.CR & stm32.RCC_CR_PLLRDY) == 0 {
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}
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// Configure Flash prefetch, Instruction cache, Data cache and wait state
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stm32.FLASH.ACR = stm32.FLASH_ACR_ICEN | stm32.FLASH_ACR_DCEN | (5 << stm32.FLASH_ACR_LATENCY_Pos)
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// Select the main PLL as system clock source
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stm32.RCC.CFGR &^= stm32.RCC_CFGR_SW0 | stm32.RCC_CFGR_SW1
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stm32.RCC.CFGR |= (0x2 << stm32.RCC_CFGR_SW0_Pos)
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for (stm32.RCC.CFGR & (0x3 << stm32.RCC_CFGR_SWS0_Pos)) != (0x2 << stm32.RCC_CFGR_SWS0_Pos) {
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}
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} else {
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// If HSE failed to start up, the application will have wrong clock configuration
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for {
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}
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}
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// Enable the CCM RAM clock
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stm32.RCC.AHB1ENR |= (1 << 20)
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}
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const tickMicros = 1000
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var (
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// tick in milliseconds
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tickCount timeUnit
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)
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//go:volatile
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type isrFlag bool
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var timerWakeup isrFlag
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// Enable the TIM3 clock.(sleep count)
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func initTIM3() {
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stm32.RCC.APB1ENR |= stm32.RCC_APB1ENR_TIM3EN
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arm.SetPriority(stm32.IRQ_TIM3, 0xc3)
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arm.EnableIRQ(stm32.IRQ_TIM3)
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}
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// Enable the TIM7 clock.(tick count)
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func initTIM7() {
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stm32.RCC.APB1ENR |= stm32.RCC_APB1ENR_TIM7EN
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// CK_INT = APB1 x2 = 84mhz
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stm32.TIM7.PSC = 84000000/10000 - 1 // 84mhz to 10khz(0.1ms)
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stm32.TIM7.ARR = stm32.RegValue(10) - 1 // interrupt per 1ms
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// Enable the hardware interrupt.
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stm32.TIM7.DIER |= stm32.TIM_DIER_UIE
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// Enable the timer.
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stm32.TIM7.CR1 |= stm32.TIM_CR1_CEN
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arm.SetPriority(stm32.IRQ_TIM7, 0xc1)
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arm.EnableIRQ(stm32.IRQ_TIM7)
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}
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const asyncScheduler = false
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// sleepTicks should sleep for specific number of microseconds.
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func sleepTicks(d timeUnit) {
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timerSleep(uint32(d))
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}
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// number of ticks (microseconds) since start.
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func ticks() timeUnit {
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// milliseconds to microseconds
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return tickCount * 1000
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}
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// ticks are in microseconds
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func timerSleep(ticks uint32) {
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timerWakeup = false
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// CK_INT = APB1 x2 = 84mhz
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// prescale counter down from 84mhz to 10khz aka 0.1 ms frequency.
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stm32.TIM3.PSC = 84000000/10000 - 1 // 8399
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// set duty aka duration
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arr := (ticks / 100) - 1 // convert from microseconds to 0.1 ms
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if arr == 0 {
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arr = 1 // avoid blocking
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}
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stm32.TIM3.ARR = stm32.RegValue(arr)
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// Enable the hardware interrupt.
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stm32.TIM3.DIER |= stm32.TIM_DIER_UIE
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// Enable the timer.
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stm32.TIM3.CR1 |= stm32.TIM_CR1_CEN
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// wait till timer wakes up
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for !timerWakeup {
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arm.Asm("wfi")
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}
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}
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//go:export TIM3_IRQHandler
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func handleTIM3() {
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if (stm32.TIM3.SR & stm32.TIM_SR_UIF) > 0 {
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// Disable the timer.
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stm32.TIM3.CR1 &^= stm32.TIM_CR1_CEN
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// clear the update flag
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stm32.TIM3.SR &^= stm32.TIM_SR_UIF
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// timer was triggered
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timerWakeup = true
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}
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}
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//go:export TIM7_IRQHandler
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func handleTIM7() {
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if (stm32.TIM7.SR & stm32.TIM_SR_UIF) > 0 {
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// clear the update flag
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stm32.TIM7.SR &^= stm32.TIM_SR_UIF
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tickCount++
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}
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}
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