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https://github.com/tinygo-org/tinygo.git
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esp32: implement flash XIP (execute-in-place) support
Add full flash XIP support for ESP32, enabling code and read-only data to execute/load directly from flash via the MMU cache rather than consuming precious SRAM. This increases available RAM from ~328KB to effectively unlimited for code/rodata, while keeping ~121KB for the Go heap. Changes: - src/device/esp/esp32.S: Add MMU initialization in call_start_cpu0 - Call ROM bootloader mmu_init() and cache_flash_mmu_set() to map DROM/IROM - Enable flash cache via ROM Cache_Read_Enable() - Fix tinygo_scanCurrentStack to spill all register windows for GC - targets/esp32-interrupts.S: Add exception diagnostics - targets/esp32.ld: Major linker script restructure for XIP - Add DROM (4MB @ 0x3F400000) and IROM (4MB @ 0x400D0000) regions - Move .rodata to DROM, main .text to IROM (both flash-mapped) - Keep boot code, vectors, and WiFi blob IRAM sections in SRAM0 - Create WiFi arena in SRAM1 pool 7/6 (64KB @ 0x3FFF0000) - Move .bss and heap to SRAM2 (200KB @ 0x3FFAE000), avoiding ROM/MAC regions - Add _drom_flash_addr variable (patched by builder with flash offset) - targets/esp32.json: Add linker wrap flags for malloc/free and WiFi functions Signed-off-by: deadprogram <ron@hybridgroup.com>
This commit is contained in:
deadprogram
+239
-4
@@ -10,6 +10,49 @@
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.section .text.call_start_cpu0
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1:
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.long _stack_top
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.Lmain_addr:
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.long main
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.Lrom_mmu_init:
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.long 0x400095a4 // mmu_init(int cpu_no)
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.Lrom_cache_flash_mmu_set:
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.long 0x400095e0 // cache_flash_mmu_set(cpu, pid, vaddr, paddr, pgsz, pgcnt)
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.Lrom_Cache_Read_Enable:
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.long 0x40009a84 // Cache_Read_Enable(int cpu_no)
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.Lrom_Cache_Read_Disable:
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.long 0x40009ab8 // Cache_Read_Disable(int cpu_no)
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.Lrom_Cache_Flush:
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.long 0x40009a14 // Cache_Flush(int cpu_no)
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.Lrodata_start:
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.long _rodata_start
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.Lrodata_end:
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.long _rodata_end
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.Ltext_start:
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.long _text_start
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.Ltext_end:
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.long _text_end
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.Ldport_pro_cache_ctrl1:
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.long 0x3FF00044 // DPORT_PRO_CACHE_CTRL1_REG
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.Ldrom_paddr_ptr:
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.long _drom_flash_addr // pointer to builder-patched DROM flash offset
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.Ldrom_vaddr:
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.long 0x3F400000 // DROM virtual base address
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.Lirom_vaddr:
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.long 0x400D0000 // IROM virtual base address
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.Lmmu_table_base:
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.long 0x3FF10000 // PRO CPU Flash MMU table
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.Lrtc_wdt_protect:
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.long 0x3FF480A4 // RTC_CNTL_WDTWPROTECT_REG
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.Lrtc_wdt_key:
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.long 0x50D83AA1 // WDT write-protect key
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.Lrtc_wdt_config0:
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.long 0x3FF4808C // RTC_CNTL_WDTCONFIG0_REG
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.Ltimg0_wdt_protect:
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.long 0x3FF5F064 // TIMG0_WDTWPROTECT_REG
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.Ltimg0_wdt_config0:
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.long 0x3FF5F048 // TIMG0_WDTCONFIG0_REG
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.Lvector_table:
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.long _vector_table
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.global call_start_cpu0
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call_start_cpu0:
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// We need to set the stack pointer to a different value. This is somewhat
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@@ -47,11 +90,203 @@ call_start_cpu0:
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wsr.cpenable a2
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rsync
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// Jump to the runtime start function written in Go.
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call4 main
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// Disable the RTC and TIMG0 watchdogs before configuring the flash cache.
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// The ROM bootloader leaves them running; a fault during cache setup would
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// otherwise reset the chip. The Go runtime re-disables them once it starts.
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l32r a2, .Lrtc_wdt_protect
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l32r a3, .Lrtc_wdt_key
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s32i a3, a2, 0 // unlock WDT write-protect
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memw
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l32r a2, .Lrtc_wdt_config0
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movi a3, 0
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s32i a3, a2, 0 // disable WDT (write 0 to config0)
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memw
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// Disable TG0 WDT (Timer Group 0 Main Watchdog).
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// TIMG0_WDTWPROTECT_REG = 0x3FF5F064, TIMG0_WDTCONFIG0_REG = 0x3FF5F048
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l32r a2, .Ltimg0_wdt_protect
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l32r a3, .Lrtc_wdt_key // same unlock key 0x50D83AA1
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s32i a3, a2, 0
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memw
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l32r a2, .Ltimg0_wdt_config0
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movi a3, 0
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s32i a3, a2, 0
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memw
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// Set VECBASE to our vector table. Must happen before any callx4 so that
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// register-window overflow exceptions route to our handlers.
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l32r a2, .Lvector_table
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wsr.vecbase a2
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rsync
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// Clear PS.EXCM so window overflow exceptions work properly.
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rsr.ps a2
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movi a3, ~0x1F
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and a2, a2, a3
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movi a3, 0x20 // PS.UM = 1
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or a2, a2, a3
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wsr.ps a2
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rsync
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// ---- Configure flash cache and MMU ----
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// The ROM bootloader only loaded IRAM/DRAM segments. We must now set up
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// the ICache MMU to map DROM (.rodata) and IROM (.text) from flash.
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// 0. Disable cache and flush before reconfiguring MMU.
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// The ROM bootloader may leave the cache enabled.
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movi a6, 0 // cpu_no = 0
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mov a5, a1
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l32r a4, .Lrom_Cache_Read_Disable
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callx4 a4
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movi a6, 0 // cpu_no = 0
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mov a5, a1
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l32r a4, .Lrom_Cache_Flush
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callx4 a4
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// 1. Reset MMU tables for PRO CPU (clear all entries to invalid).
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movi a6, 0 // cpu_no = 0 (PRO)
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mov a5, a1
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l32r a4, .Lrom_mmu_init
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callx4 a4
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// 2. Map DROM pages via ROM cache_flash_mmu_set:
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// vaddr=0x3F400000, paddr=0x10000, page_size=64KB, count=ceil(size/64KB)
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l32r a2, .Lrodata_end
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l32r a3, .Lrodata_start
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sub a2, a2, a3 // a2 = rodata size in bytes
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beqz a2, .Lskip_drom // skip if no rodata
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addi a2, a2, -1
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srli a2, a2, 16
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addi a2, a2, 1 // a2 = drom page count
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// cache_flash_mmu_set(cpu=0, pid=0, vaddr, paddr, psize=64, num)
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movi a6, 0
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movi a7, 0
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l32r a8, .Ldrom_vaddr // 0x3F400000
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l32r a9, .Ldrom_paddr_ptr
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l32i a9, a9, 0 // a9 = DROM flash offset (builder-patched)
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movi a10, 64
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mov a11, a2
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mov a5, a1
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l32r a4, .Lrom_cache_flash_mmu_set
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callx4 a4
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.Lskip_drom:
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// 3. Map IROM pages via ROM cache_flash_mmu_set:
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// vaddr=0x400D0000, paddr=0x10000 + drom_pages*64KB
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l32r a2, .Ltext_end
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l32r a3, .Ltext_start
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sub a2, a2, a3 // a2 = text size in bytes
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beqz a2, .Lskip_irom // skip if no text
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addi a2, a2, -1
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srli a2, a2, 16
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addi a2, a2, 1 // a2 = irom page count
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// Compute IROM paddr into a3 = DROM flash offset + drom_pages * 64KB
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l32r a9, .Lrodata_end
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l32r a3, .Lrodata_start
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sub a9, a9, a3 // a9 = rodata size
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l32r a3, .Ldrom_paddr_ptr
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l32i a3, a3, 0 // a3 = DROM flash offset (builder-patched)
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beqz a9, .Lirom_paddr_ready
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addi a9, a9, -1
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srli a9, a9, 16
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addi a9, a9, 1 // a9 = drom page count
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slli a9, a9, 16 // a9 = drom_pages * 64KB
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add a3, a3, a9 // a3 = drom_flash_addr + drom_pages * 64KB
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.Lirom_paddr_ready:
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movi a6, 0
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movi a7, 0
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l32r a8, .Lirom_vaddr // 0x400D0000
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mov a9, a3 // irom paddr
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movi a10, 64
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mov a11, a2
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mov a5, a1
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l32r a4, .Lrom_cache_flash_mmu_set
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callx4 a4
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.Lskip_irom:
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// 4. Unmask DROM0 and IRAM0 cache buses in DPORT_PRO_CACHE_CTRL1_REG:
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// bit 4: PRO_CACHE_MASK_DROM0 (data flash, 0x3F400000)
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// bit 0: PRO_CACHE_MASK_IRAM0 (instruction flash, 0x400D0000 window)
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l32r a2, .Ldport_pro_cache_ctrl1
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l32i a3, a2, 0
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movi a4, ~0x11 // clear bit 0 (IRAM0) and bit 4 (DROM0)
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and a3, a3, a4
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s32i a3, a2, 0
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memw
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// 5. Enable flash cache for PRO CPU.
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movi a6, 0 // cpu_no = 0
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mov a5, a1
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l32r a4, .Lrom_Cache_Read_Enable
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callx4 a4
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isync
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// ---- Jump to main (in IROM/flash, now accessible) ----
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mov a5, a1
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l32r a4, .Lmain_addr
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callx4 a4
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// If main returns, loop forever.
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1: j 1b
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// -----------------------------------------------------------------------
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// tinygo_scanCurrentStack — Spill all Xtensa register windows to the
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// stack, then call tinygo_scanstack(sp) so the conservative GC can
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// discover live heap pointers that are currently in physical registers.
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//
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// On RISC-V / ARM the equivalent function pushes callee-saved registers
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// before the call. On Xtensa windowed ABI the same effect is achieved
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// by forcing hardware window-overflow for every occupied pane: each
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// overflow saves the four registers in that pane to the stack frame
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// pointed to by the pane's a1 (sp). After all panes are flushed, a
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// scan from the current sp to stackTop covers every live value.
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//
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// Without this spill the conservative GC misses heap pointers held only
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// in physical registers, frees live objects, and later crashes jumping
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// through a freed/garbage function pointer (e.g. a goroutine trampoline).
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// -----------------------------------------------------------------------
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.section .text.tinygo_scanCurrentStack
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.global tinygo_scanCurrentStack
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tinygo_scanCurrentStack:
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// TODO: save callee saved registers on the stack
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j tinygo_scanstack
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entry a1, 48
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// Disable interrupts while flushing register windows.
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rsr a4, PS
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s32i a4, a1, 0 // save PS for later restore
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rsil a4, 3 // XCHAL_EXCM_LEVEL
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// Flush all register windows using recursive call4.
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// For NAREG=64 (16 panes), 15 recursive levels cover all panes
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// except the current one (which is kept active).
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movi a6, 15
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call4 .Lscan_spill
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// Restore interrupts.
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l32i a4, a1, 0
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wsr.ps a4
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rsync
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// Pass current sp to tinygo_scanstack.
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// call4 maps caller's a5→callee's a1 (stack ptr for callee's entry)
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// and caller's a6→callee's a2 (first argument = sp).
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mov a5, a1 // callee's a1 = valid stack pointer
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mov a6, a1 // callee's a2 = sp argument
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call4 tinygo_scanstack
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retw
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.balign 4
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.Lscan_spill:
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entry a1, 16
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beqz a2, .Lscan_spill_done
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addi a2, a2, -1
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mov a6, a2
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call4 .Lscan_spill
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.Lscan_spill_done:
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retw
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