mirror of
https://github.com/tinygo-org/tinygo.git
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Minimal NXP/Teensy support
This commit is contained in:
Ethan Reesor
Ron Evans
@@ -0,0 +1,5 @@
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// +build nxp
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package runtime
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type timeUnit int64
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@@ -0,0 +1,342 @@
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// Derivative work of Teensyduino Core Library
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// http://www.pjrc.com/teensy/
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// Copyright (c) 2017 PJRC.COM, LLC.
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//
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// Permission is hereby granted, free of charge, to any person obtaining
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// a copy of this software and associated documentation files (the
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// "Software"), to deal in the Software without restriction, including
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// without limitation the rights to use, copy, modify, merge, publish,
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// distribute, sublicense, and/or sell copies of the Software, and to
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// permit persons to whom the Software is furnished to do so, subject to
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// the following conditions:
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//
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// 1. The above copyright notice and this permission notice shall be
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// included in all copies or substantial portions of the Software.
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//
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// 2. If the Software is incorporated into a build system that allows
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// selection among a list of target devices, then similar target
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// devices manufactured by PJRC.COM must be included in the list of
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// target devices and selectable in the same manner.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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// +build nxp,mk66f18
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package runtime
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import (
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"device/arm"
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"device/nxp"
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"machine"
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"runtime/volatile"
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)
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const (
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WDOG_UNLOCK_SEQ1 = 0xC520
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WDOG_UNLOCK_SEQ2 = 0xD928
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DEFAULT_FTM_MOD = 61440 - 1
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DEFAULT_FTM_PRESCALE = 1
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)
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var (
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SIM_SOPT2_IRC48SEL = nxp.SIM_SOPT2_PLLFLLSEL(3)
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SMC_PMCTRL_HSRUN = nxp.SMC_PMCTRL_RUNM(3)
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SMC_PMSTAT_HSRUN = nxp.SMC_PMSTAT_PMSTAT(0x80)
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)
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//go:section .resetHandler
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//go:export Reset_Handler
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func main() {
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nxp.WDOG.UNLOCK.Set(WDOG_UNLOCK_SEQ1)
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nxp.WDOG.UNLOCK.Set(WDOG_UNLOCK_SEQ2)
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arm.Asm("nop")
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arm.Asm("nop")
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startupEarlyHook()
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// enable clocks to always-used peripherals
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nxp.SIM.SCGC3.Set(nxp.SIM_SCGC3_ADC1 | nxp.SIM_SCGC3_FTM2 | nxp.SIM_SCGC3_FTM3)
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nxp.SIM.SCGC5.Set(0x00043F82) // clocks active to all GPIO
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nxp.SIM.SCGC6.Set(nxp.SIM_SCGC6_RTC | nxp.SIM_SCGC6_FTM0 | nxp.SIM_SCGC6_FTM1 | nxp.SIM_SCGC6_ADC0 | nxp.SIM_SCGC6_FTF)
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nxp.SystemControl.CPACR.Set(0x00F00000)
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nxp.LMEM.PCCCR.Set(0x85000003)
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// release I/O pins hold, if we woke up from VLLS mode
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if nxp.PMC.REGSC.HasBits(nxp.PMC_REGSC_ACKISO) {
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nxp.PMC.REGSC.SetBits(nxp.PMC_REGSC_ACKISO)
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}
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// since this is a write once register, make it visible to all F_CPU's
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// so we can into other sleep modes in the future at any speed
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nxp.SMC.PMPROT.Set(nxp.SMC_PMPROT_AHSRUN | nxp.SMC_PMPROT_AVLP | nxp.SMC_PMPROT_ALLS | nxp.SMC_PMPROT_AVLLS)
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preinit()
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// copy the vector table to RAM default all interrupts to medium priority level
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// for (i=0; i < NVIC_NUM_INTERRUPTS + 16; i++) _VectorsRam[i] = _VectorsFlash[i];
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for i := uint32(0); i <= nxp.IRQ_max; i++ {
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arm.SetPriority(i, 128)
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}
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// SCB_VTOR = (uint32_t)_VectorsRam; // use vector table in RAM
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// hardware always starts in FEI mode
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// C1[CLKS] bits are written to 00
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// C1[IREFS] bit is written to 1
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// C6[PLLS] bit is written to 0
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// MCG_SC[FCDIV] defaults to divide by two for internal ref clock
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// I tried changing MSG_SC to divide by 1, it didn't work for me
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// enable capacitors for crystal
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nxp.OSC.CR.Set(nxp.OSC_CR_SC8P | nxp.OSC_CR_SC2P | nxp.OSC_CR_ERCLKEN)
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// enable osc, 8-32 MHz range, low power mode
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nxp.MCG.C2.Set(uint8(nxp.MCG_C2_RANGE(2) | nxp.MCG_C2_EREFS))
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// switch to crystal as clock source, FLL input = 16 MHz / 512
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nxp.MCG.C1.Set(uint8(nxp.MCG_C1_CLKS(2) | nxp.MCG_C1_FRDIV(4)))
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// wait for crystal oscillator to begin
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for !nxp.MCG.S.HasBits(nxp.MCG_S_OSCINIT0) {
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}
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// wait for FLL to use oscillator
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for nxp.MCG.S.HasBits(nxp.MCG_S_IREFST) {
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}
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// wait for MCGOUT to use oscillator
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for (nxp.MCG.S.Get() & nxp.MCG_S_CLKST_Msk) != nxp.MCG_S_CLKST(2) {
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}
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// now in FBE mode
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// C1[CLKS] bits are written to 10
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// C1[IREFS] bit is written to 0
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// C1[FRDIV] must be written to divide xtal to 31.25-39 kHz
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// C6[PLLS] bit is written to 0
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// C2[LP] is written to 0
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// we need faster than the crystal, turn on the PLL (F_CPU > 120000000)
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nxp.SMC.PMCTRL.Set(SMC_PMCTRL_HSRUN) // enter HSRUN mode
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for nxp.SMC.PMSTAT.Get() != SMC_PMSTAT_HSRUN {
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} // wait for HSRUN
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nxp.MCG.C5.Set(nxp.MCG_C5_PRDIV(1))
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nxp.MCG.C6.Set(nxp.MCG_C6_PLLS | nxp.MCG_C6_VDIV(29))
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// wait for PLL to start using xtal as its input
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for !nxp.MCG.S.HasBits(nxp.MCG_S_PLLST) {
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}
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// wait for PLL to lock
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for !nxp.MCG.S.HasBits(nxp.MCG_S_LOCK0) {
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}
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// now we're in PBE mode
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// now program the clock dividers
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// config divisors: 180 MHz core, 60 MHz bus, 25.7 MHz flash, USB = IRC48M
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nxp.SIM.CLKDIV1.Set(nxp.SIM_CLKDIV1_OUTDIV1(0) | nxp.SIM_CLKDIV1_OUTDIV2(2) | nxp.SIM_CLKDIV1_OUTDIV4(6))
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nxp.SIM.CLKDIV2.Set(nxp.SIM_CLKDIV2_USBDIV(0))
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// switch to PLL as clock source, FLL input = 16 MHz / 512
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nxp.MCG.C1.Set(nxp.MCG_C1_CLKS(0) | nxp.MCG_C1_FRDIV(4))
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// wait for PLL clock to be used
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for (nxp.MCG.S.Get() & nxp.MCG_S_CLKST_Msk) != nxp.MCG_S_CLKST(3) {
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}
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// now we're in PEE mode
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// trace is CPU clock, CLKOUT=OSCERCLK0
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// USB uses IRC48
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nxp.SIM.SOPT2.Set(nxp.SIM_SOPT2_USBSRC | SIM_SOPT2_IRC48SEL | nxp.SIM_SOPT2_TRACECLKSEL | nxp.SIM_SOPT2_CLKOUTSEL(6))
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// If the RTC oscillator isn't enabled, get it started. For Teensy 3.6
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// we don't do this early. See comment above about slow rising power.
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if !nxp.RTC.CR.HasBits(nxp.RTC_CR_OSCE) {
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nxp.RTC.SR.Set(0)
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nxp.RTC.CR.Set(nxp.RTC_CR_SC16P | nxp.RTC_CR_SC4P | nxp.RTC_CR_OSCE)
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}
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// initialize the SysTick counter
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nxp.SysTick.RVR.Set((machine.CPUFrequency() / 1000) - 1)
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nxp.SysTick.CVR.Set(0)
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nxp.SysTick.CSR.Set(nxp.SysTick_CSR_CLKSOURCE | nxp.SysTick_CSR_TICKINT | nxp.SysTick_CSR_ENABLE)
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nxp.SystemControl.SHPR3.Set(0x20200000) // Systick = priority 32
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arm.Asm("CPSIE i")
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initTeensyInternal()
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startupLateHook()
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// initAll()
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runMain()
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// abort()
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for {
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}
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}
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// ported _init_Teensyduino_internal_ from pins_teensy.c from teensy3 core libraries
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func initTeensyInternal() {
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arm.EnableIRQ(nxp.IRQ_PORTA)
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arm.EnableIRQ(nxp.IRQ_PORTB)
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arm.EnableIRQ(nxp.IRQ_PORTC)
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arm.EnableIRQ(nxp.IRQ_PORTD)
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arm.EnableIRQ(nxp.IRQ_PORTE)
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nxp.FTM0.CNT.Set(0)
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nxp.FTM0.MOD.Set(DEFAULT_FTM_MOD)
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nxp.FTM0.C0SC.Set(0x28) // MSnB:MSnA = 10, ELSnB:ELSnA = 10
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nxp.FTM0.C1SC.Set(0x28)
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nxp.FTM0.C2SC.Set(0x28)
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nxp.FTM0.C3SC.Set(0x28)
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nxp.FTM0.C4SC.Set(0x28)
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nxp.FTM0.C5SC.Set(0x28)
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nxp.FTM0.C6SC.Set(0x28)
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nxp.FTM0.C7SC.Set(0x28)
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nxp.FTM3.C0SC.Set(0x28)
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nxp.FTM3.C1SC.Set(0x28)
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nxp.FTM3.C2SC.Set(0x28)
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nxp.FTM3.C3SC.Set(0x28)
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nxp.FTM3.C4SC.Set(0x28)
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nxp.FTM3.C5SC.Set(0x28)
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nxp.FTM3.C6SC.Set(0x28)
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nxp.FTM3.C7SC.Set(0x28)
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nxp.FTM0.SC.Set(nxp.FTM_SC_CLKS(1) | nxp.FTM_SC_PS(DEFAULT_FTM_PRESCALE))
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nxp.FTM1.CNT.Set(0)
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nxp.FTM1.MOD.Set(DEFAULT_FTM_MOD)
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nxp.FTM1.C0SC.Set(0x28)
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nxp.FTM1.C1SC.Set(0x28)
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nxp.FTM1.SC.Set(nxp.FTM_SC_CLKS(1) | nxp.FTM_SC_PS(DEFAULT_FTM_PRESCALE))
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// nxp.FTM2.CNT.Set(0)
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// nxp.FTM2.MOD.Set(DEFAULT_FTM_MOD)
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// nxp.FTM2.C0SC.Set(0x28)
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// nxp.FTM2.C1SC.Set(0x28)
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// nxp.FTM2.SC.Set(nxp.FTM_SC_CLKS(1) | nxp.FTM_SC_PS(DEFAULT_FTM_PRESCALE))
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nxp.FTM3.CNT.Set(0)
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nxp.FTM3.MOD.Set(DEFAULT_FTM_MOD)
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nxp.FTM3.C0SC.Set(0x28)
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nxp.FTM3.C1SC.Set(0x28)
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nxp.FTM3.SC.Set(nxp.FTM_SC_CLKS(1) | nxp.FTM_SC_PS(DEFAULT_FTM_PRESCALE))
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nxp.SIM.SCGC2.SetBits(nxp.SIM_SCGC2_TPM1)
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nxp.SIM.SOPT2.SetBits(nxp.SIM_SOPT2_TPMSRC(2))
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nxp.TPM1.CNT.Set(0)
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nxp.TPM1.MOD.Set(32767)
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nxp.TPM1.C0SC.Set(0x28)
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nxp.TPM1.C1SC.Set(0x28)
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nxp.TPM1.SC.Set(nxp.FTM_SC_CLKS(1) | nxp.FTM_SC_PS(0))
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// analog_init();
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// #if !defined(TEENSY_INIT_USB_DELAY_BEFORE)
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// #if TEENSYDUINO >= 142
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// #define TEENSY_INIT_USB_DELAY_BEFORE 25
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// #else
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// #define TEENSY_INIT_USB_DELAY_BEFORE 50
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// #endif
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// #endif
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// #if !defined(TEENSY_INIT_USB_DELAY_AFTER)
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// #if TEENSYDUINO >= 142
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// #define TEENSY_INIT_USB_DELAY_AFTER 275
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// #else
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// #define TEENSY_INIT_USB_DELAY_AFTER 350
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// #endif
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// #endif
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// // for background about this startup delay, please see these conversations
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// // https://forum.pjrc.com/threads/36606-startup-time-(400ms)?p=113980&viewfull=1#post113980
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// // https://forum.pjrc.com/threads/31290-Teensey-3-2-Teensey-Loader-1-24-Issues?p=87273&viewfull=1#post87273
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// delay(TEENSY_INIT_USB_DELAY_BEFORE);
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// usb_init();
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// delay(TEENSY_INIT_USB_DELAY_AFTER);
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}
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func startupEarlyHook() {
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// TODO allow override
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// > programs using the watchdog timer or needing to initialize hardware as
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// > early as possible can implement startup_early_hook()
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nxp.WDOG.STCTRLH.Set(nxp.WDOG_STCTRLH_ALLOWUPDATE)
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}
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func startupLateHook() {
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// TODO allow override
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}
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//go:noinline
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func runMain() {
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// this is a separate function to ensure that Reset_Handler fits in 0x230 bytes regardless of whether (user) main requires scheduling
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callMain()
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}
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func putchar(c byte) {
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}
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// ???
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const asyncScheduler = false
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// microseconds per tick
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const tickMicros = 1000
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// number of ticks since boot
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var tickMilliCount uint32
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//go:export SysTick_Handler
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func tickHandler() {
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volatile.StoreUint32(&tickMilliCount, volatile.LoadUint32(&tickMilliCount)+1)
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}
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// ticks are in microseconds
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func ticks() timeUnit {
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m := arm.DisableInterrupts()
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current := nxp.SysTick.CVR.Get()
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count := tickMilliCount
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istatus := nxp.SystemControl.ICSR.Get()
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arm.EnableInterrupts(m)
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if istatus&nxp.SystemControl_ICSR_PENDSTSET != 0 && current > 50 {
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count++
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}
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current = ((machine.CPUFrequency() / tickMicros) - 1) - current
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return timeUnit(count*tickMicros + current/(machine.CPUFrequency()/1000000))
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}
|
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|
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// sleepTicks spins for a number of microseconds
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func sleepTicks(d timeUnit) {
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// TODO actually sleep
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if d <= 0 {
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return
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}
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start := ticks()
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ms := d / 1000
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for {
|
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for ticks()-start >= 1000 {
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ms--
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if ms <= 0 {
|
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return
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}
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start += 1000
|
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}
|
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// Gosched()
|
||||
}
|
||||
}
|
||||
|
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func Sleep(d int64) {
|
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sleepTicks(timeUnit(d))
|
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}
|
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|
||||
// func abort() {
|
||||
// for {
|
||||
// // keep polling some communication while in fault
|
||||
// // mode, so we don't completely die.
|
||||
// if nxp.SIM.SCGC4.HasBits(nxp.SIM_SCGC4_USBOTG) usb_isr();
|
||||
// if nxp.SIM.SCGC4.HasBits(nxp.SIM_SCGC4_UART0) uart0_status_isr();
|
||||
// if nxp.SIM.SCGC4.HasBits(nxp.SIM_SCGC4_UART1) uart1_status_isr();
|
||||
// if nxp.SIM.SCGC4.HasBits(nxp.SIM_SCGC4_UART2) uart2_status_isr();
|
||||
// }
|
||||
// }
|
||||
@@ -0,0 +1,84 @@
|
||||
// +build nxp,mk66f18
|
||||
|
||||
package volatile
|
||||
|
||||
import "unsafe"
|
||||
|
||||
const registerBase = 0x40000000
|
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const registerEnd = 0x40100000
|
||||
const bitbandBase = 0x42000000
|
||||
const ptrBytes = unsafe.Sizeof(uintptr(0))
|
||||
|
||||
//go:inline
|
||||
func bitbandAddress(reg uintptr, bit uintptr) uintptr {
|
||||
if bit > ptrBytes*8 {
|
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panic("invalid bit position")
|
||||
}
|
||||
if reg < registerBase || reg >= registerEnd {
|
||||
panic("register is out of range")
|
||||
}
|
||||
return (reg-registerBase)*ptrBytes*8 + bit*ptrBytes + bitbandBase
|
||||
}
|
||||
|
||||
// Special types that causes loads/stores to be volatile (necessary for
|
||||
// memory-mapped registers).
|
||||
type BitRegister struct {
|
||||
Reg uint32
|
||||
}
|
||||
|
||||
// Get returns the of the mapped register bit. It is the volatile equivalent of:
|
||||
//
|
||||
// *r.Reg
|
||||
//
|
||||
//go:inline
|
||||
func (r *BitRegister) Get() bool {
|
||||
return LoadUint32(&r.Reg) != 0
|
||||
}
|
||||
|
||||
// Set sets the mapped register bit. It is the volatile equivalent of:
|
||||
//
|
||||
// *r.Reg = 1
|
||||
//
|
||||
//go:inline
|
||||
func (r *BitRegister) Set() {
|
||||
StoreUint32(&r.Reg, 1)
|
||||
}
|
||||
|
||||
// Clear clears the mapped register bit. It is the volatile equivalent of:
|
||||
//
|
||||
// *r.Reg = 0
|
||||
//
|
||||
//go:inline
|
||||
func (r *BitRegister) Clear() {
|
||||
StoreUint32(&r.Reg, 0)
|
||||
}
|
||||
|
||||
// Bit maps bit N of register R to the corresponding bitband address. Bit panics
|
||||
// if R is not an AIPS or GPIO register or if N is out of range (greater than
|
||||
// the number of bits in a register minus one).
|
||||
//
|
||||
// go:inline
|
||||
func (r *Register8) Bit(bit uintptr) *BitRegister {
|
||||
ptr := bitbandAddress(uintptr(unsafe.Pointer(&r.Reg)), bit)
|
||||
return (*BitRegister)(unsafe.Pointer(ptr))
|
||||
}
|
||||
|
||||
// Bit maps bit N of register R to the corresponding bitband address. Bit panics
|
||||
// if R is not an AIPS or GPIO register or if N is out of range (greater than
|
||||
// the number of bits in a register minus one).
|
||||
//
|
||||
// go:inline
|
||||
func (r *Register16) Bit(bit uintptr) *BitRegister {
|
||||
ptr := bitbandAddress(uintptr(unsafe.Pointer(&r.Reg)), bit)
|
||||
return (*BitRegister)(unsafe.Pointer(ptr))
|
||||
}
|
||||
|
||||
// Bit maps bit N of register R to the corresponding bitband address. Bit panics
|
||||
// if R is not an AIPS or GPIO register or if N is out of range (greater than
|
||||
// the number of bits in a register minus one).
|
||||
//
|
||||
// go:inline
|
||||
func (r *Register32) Bit(bit uintptr) *BitRegister {
|
||||
ptr := bitbandAddress(uintptr(unsafe.Pointer(&r.Reg)), bit)
|
||||
return (*BitRegister)(unsafe.Pointer(ptr))
|
||||
}
|
||||
Reference in New Issue
Block a user