mirror of
https://github.com/tinygo-org/tinygo.git
synced 2026-08-14 07:53:40 +00:00
Merge branch 'dev' into feature/usb-common
This commit is contained in:
ardnew
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["atsamd21g18a"],
|
||||
"build-tags": ["arduino_mkr1000"],
|
||||
"serial": "usb",
|
||||
"flash-command": "bossac -i -e -w -v -R -U --port={port} --offset=0x2000 {bin}",
|
||||
"flash-1200-bps-reset": "true"
|
||||
}
|
||||
|
||||
@@ -2,5 +2,6 @@
|
||||
"inherits": ["atsamd21g18a"],
|
||||
"build-tags": ["arduino_nano33"],
|
||||
"flash-command": "bossac -i -e -w -v -R -U --port={port} --offset=0x2000 {bin}",
|
||||
"serial-port": ["acm:2341:8057", "acm:2341:0057"],
|
||||
"flash-1200-bps-reset": "true"
|
||||
}
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["atsamd21g18a"],
|
||||
"build-tags": ["arduino_zero"],
|
||||
"serial": "usb",
|
||||
"flash-command": "bossac -i -e -w -v -R -U --port={port} --offset=0x2000 {bin}",
|
||||
"flash-1200-bps-reset": "true"
|
||||
}
|
||||
|
||||
@@ -6,5 +6,6 @@
|
||||
"-Wl,--defsym=_stack_size=512"
|
||||
],
|
||||
"flash-command": "avrdude -c arduino -p atmega328p -P {port} -U flash:w:{hex}:i",
|
||||
"serial-port": ["acm:2341:0043", "acm:2341:0001", "acm:2a03:0043", "acm:2341:0243"],
|
||||
"emulator": ["simavr", "-m", "atmega328p", "-f", "16000000"]
|
||||
}
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
"inherits": ["avr"],
|
||||
"cpu": "atmega1280",
|
||||
"build-tags": ["atmega1280", "atmega"],
|
||||
"serial": "uart",
|
||||
"cflags": [
|
||||
"-mmcu=atmega1280"
|
||||
],
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
"inherits": ["avr"],
|
||||
"cpu": "atmega1284p",
|
||||
"build-tags": ["atmega1284p", "atmega"],
|
||||
"serial": "uart",
|
||||
"cflags": [
|
||||
"-mmcu=atmega1284p"
|
||||
],
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
"inherits": ["avr"],
|
||||
"cpu": "atmega2560",
|
||||
"build-tags": ["atmega2560", "atmega"],
|
||||
"serial": "uart",
|
||||
"cflags": [
|
||||
"-mmcu=atmega2560"
|
||||
],
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
"inherits": ["avr"],
|
||||
"cpu": "atmega328p",
|
||||
"build-tags": ["atmega328p", "atmega", "avr5"],
|
||||
"serial": "uart",
|
||||
"cflags": [
|
||||
"-mmcu=atmega328p"
|
||||
],
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["cortex-m0plus"],
|
||||
"build-tags": ["atsamd21e18a", "atsamd21e18", "atsamd21", "sam"],
|
||||
"serial": "usb",
|
||||
"linkerscript": "targets/atsamd21.ld",
|
||||
"extra-files": [
|
||||
"src/device/sam/atsamd21e18a.s"
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["cortex-m0plus"],
|
||||
"build-tags": ["atsamd21g18a", "atsamd21g18", "atsamd21", "sam"],
|
||||
"serial": "usb",
|
||||
"linkerscript": "targets/atsamd21.ld",
|
||||
"extra-files": [
|
||||
"src/device/sam/atsamd21g18a.s"
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["atsame54p20a"],
|
||||
"build-tags": ["atsame54_xpro"],
|
||||
"serial": "usb",
|
||||
"flash-method": "openocd",
|
||||
"openocd-interface": "cmsis-dap",
|
||||
"default-stack-size": 4096
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["cortex-m3"],
|
||||
"build-tags": ["bluepill", "stm32f103", "stm32f1", "stm32"],
|
||||
"serial": "uart",
|
||||
"linkerscript": "targets/stm32.ld",
|
||||
"extra-files": [
|
||||
"src/device/stm32/stm32f103.s"
|
||||
|
||||
@@ -1,8 +1,10 @@
|
||||
{
|
||||
"inherits": ["nrf52840"],
|
||||
"build-tags": ["circuitplay_bluefruit","nrf52840_reset_uf2", "softdevice", "s140v6"],
|
||||
"serial": "usb",
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"serial-port": ["acm:239a:8045", "acm:239a:45"],
|
||||
"msd-volume-name": "CPLAYBTBOOT",
|
||||
"msd-firmware-name": "firmware.uf2",
|
||||
"uf2-family-id": "0xADA52840",
|
||||
|
||||
@@ -3,6 +3,7 @@
|
||||
"build-tags": ["circuitplay_express"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"serial-port": ["acm:239a:8018", "acm:239a:18"],
|
||||
"msd-volume-name": "CPLAYBOOT",
|
||||
"msd-firmware-name": "firmware.uf2"
|
||||
}
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["nrf52840"],
|
||||
"build-tags": ["clue_alpha","nrf52840_reset_uf2", "softdevice", "s140v6"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:239a:8072", "acm:239a:0072", "acm:239a:0071", "acm:239a:8071"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "CLUEBOOT",
|
||||
|
||||
@@ -8,7 +8,7 @@
|
||||
"rtlib": "compiler-rt",
|
||||
"libc": "picolibc",
|
||||
"automatic-stack-size": true,
|
||||
"default-stack-size": 1024,
|
||||
"default-stack-size": 2048,
|
||||
"cflags": [
|
||||
"-Oz",
|
||||
"-mthumb",
|
||||
|
||||
@@ -3,6 +3,7 @@
|
||||
"cpu": "esp32",
|
||||
"build-tags": ["esp32", "esp"],
|
||||
"scheduler": "tasks",
|
||||
"serial": "uart",
|
||||
"linker": "xtensa-esp32-elf-ld",
|
||||
"default-stack-size": 2048,
|
||||
"cflags": [
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["atsamd21g18a"],
|
||||
"build-tags": ["feather_m0"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:239a:801b", "acm:239a:001b", "acm:239a:800b", "acm:239a:000b", "acm:239a:0015"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "FEATHERBOOT",
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["atsame51j19a"],
|
||||
"build-tags": ["feather_m4_can"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:239a:80cd", "acm:239a:00cd"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "FTHRCANBOOT",
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["atsamd51j19a"],
|
||||
"build-tags": ["feather_m4"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:239a:8022", "acm:239a:0022"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "FEATHERBOOT",
|
||||
|
||||
@@ -0,0 +1,12 @@
|
||||
{
|
||||
"inherits": ["nrf52840"],
|
||||
"build-tags": ["feather_nrf52840_sense","nrf52840_reset_uf2", "softdevice", "s140v6"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:239a:8087", "acm:239a:0087", "acm:239a:0088", "acm:239a:8088"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "FTHRSNSBOOT",
|
||||
"msd-firmware-name": "firmware.uf2",
|
||||
"uf2-family-id": "0xADA52840",
|
||||
"linkerscript": "targets/circuitplay-bluefruit.ld"
|
||||
}
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["nrf52840"],
|
||||
"build-tags": ["feather_nrf52840","nrf52840_reset_uf2", "softdevice", "s140v6"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:239a:8029", "acm:239a:0029", "acm:239a:002a", "acm:239a:802a"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "FTHR840BOOT",
|
||||
|
||||
@@ -0,0 +1,17 @@
|
||||
// Adafruit Feather RP2040 Stage 2 Bootloader
|
||||
|
||||
//
|
||||
// This file defines the parameters specific to the flash-chip found
|
||||
// on the Adafruit Feather RP2040. The generic implementation is in
|
||||
// rp2040-boot-stage2.S
|
||||
//
|
||||
|
||||
#define BOARD_PICO_FLASH_SPI_CLKDIV 2
|
||||
#define BOARD_CMD_READ 0xe7
|
||||
#define BOARD_QUAD_OK 1
|
||||
#define BOARD_QUAD_ENABLE_STATUS_BYTE 2
|
||||
#define BOARD_QUAD_ENABLE_BIT_MASK 2
|
||||
#define BOARD_SPLIT_STATUS_WRITE 1
|
||||
#define BOARD_WAIT_CYCLES 2
|
||||
|
||||
#include "rp2040-boot-stage2.S"
|
||||
@@ -0,0 +1,11 @@
|
||||
{
|
||||
"inherits": [
|
||||
"rp2040"
|
||||
],
|
||||
"serial": "uart",
|
||||
"build-tags": ["feather_rp2040"],
|
||||
"linkerscript": "targets/feather-rp2040.ld",
|
||||
"extra-files": [
|
||||
"targets/feather-rp2040-boot-stage2.S"
|
||||
]
|
||||
}
|
||||
@@ -0,0 +1,10 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Reserve exactly 256 bytes at start of flash for second stage bootloader */
|
||||
BOOT2_TEXT (rx) : ORIGIN = 0x10000000, LENGTH = 256
|
||||
FLASH_TEXT (rx) : ORIGIN = 0x10000000 + 256, LENGTH = 8192K - 256
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256k
|
||||
}
|
||||
|
||||
INCLUDE "targets/rp2040.ld"
|
||||
@@ -1,8 +1,8 @@
|
||||
{
|
||||
"inherits": ["cortex-m4"],
|
||||
"build-tags": ["feather_stm32f405", "stm32f405", "stm32f4", "stm32"],
|
||||
"serial": "uart",
|
||||
"automatic-stack-size": false,
|
||||
"default-stack-size": 1024,
|
||||
"linkerscript": "targets/stm32f405.ld",
|
||||
"extra-files": [
|
||||
"src/device/stm32/stm32f405.s"
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["atsamd51p20a"],
|
||||
"build-tags": ["grandcentral_m4"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:239a:8031", "acm:239a:0031", "acm:239a:0032"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "GCM4BOOT",
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["fe310"],
|
||||
"build-tags": ["hifive1b", "qemu"],
|
||||
"serial": "uart",
|
||||
"linkerscript": "targets/hifive1-qemu.ld",
|
||||
"emulator": ["qemu-system-riscv32", "-machine", "sifive_e", "-nographic", "-kernel"]
|
||||
}
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["fe310"],
|
||||
"build-tags": ["hifive1b"],
|
||||
"serial": "uart",
|
||||
"linkerscript": "targets/hifive1b.ld",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "HiFive",
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["atsamd21g18a"],
|
||||
"build-tags": ["itsybitsy_m0"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:239a:800f", "acm:239a:000f", "acm:239a:8012"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "ITSYBOOT",
|
||||
|
||||
@@ -1,8 +1,10 @@
|
||||
{
|
||||
"inherits": ["atsamd51g19a"],
|
||||
"build-tags": ["itsybitsy_m4"],
|
||||
"serial": "usb",
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"serial-port": ["acm:239a:802b", "acm:239a:002b"],
|
||||
"msd-volume-name": "ITSYM4BOOT",
|
||||
"msd-firmware-name": "firmware.uf2"
|
||||
}
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["nrf52840"],
|
||||
"build-tags": ["itsybitsy_nrf52840","nrf52840_reset_uf2", "softdevice", "s140v6"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:239A:8052", "acm:239A:0052", "acm:239A:0051", "acm:239A:8051"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "ITSY840BOOT",
|
||||
|
||||
@@ -5,6 +5,7 @@
|
||||
"build-tags": [
|
||||
"lgt92"
|
||||
],
|
||||
"serial": "uart",
|
||||
"linkerscript": "targets/stm32l072czt6.ld",
|
||||
"flash-method": "openocd",
|
||||
"openocd-interface": "stlink-v2",
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["k210"],
|
||||
"build-tags": ["maixbit"],
|
||||
"serial": "uart",
|
||||
"linkerscript": "targets/maixbit.ld",
|
||||
"flash-command": "kflash -p {port} --noansi --verbose {bin}"
|
||||
}
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["atsamd51j19a"],
|
||||
"build-tags": ["atsamd51j19a", "matrixportal_m4"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:239a:80c9", "acm:239a:00c9", "acm:239a:80ca"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "MATRIXBOOT",
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["atsamd51j19a"],
|
||||
"build-tags": ["metro_m4_airlift"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:239A:8037", "acm:239A:0037"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "METROM4BOOT",
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["nrf52833"],
|
||||
"build-tags": ["microbit_v2"],
|
||||
"serial": "uart",
|
||||
"flash-method": "msd",
|
||||
"openocd-interface": "cmsis-dap",
|
||||
"msd-volume-name": "MICROBIT",
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["nrf51"],
|
||||
"build-tags": ["microbit"],
|
||||
"serial": "uart",
|
||||
"flash-method": "msd",
|
||||
"openocd-interface": "cmsis-dap",
|
||||
"msd-volume-name": "MICROBIT",
|
||||
|
||||
@@ -0,0 +1,3 @@
|
||||
{
|
||||
"inherits": ["nano-33-ble"]
|
||||
}
|
||||
@@ -0,0 +1,9 @@
|
||||
{
|
||||
"inherits": ["nrf52840"],
|
||||
"build-tags": ["nano_33_ble", "nrf52840_reset_bossa"],
|
||||
"flash-command": "bossac_arduino2 -d -i -e -w -v -R --port={port} {bin}",
|
||||
"serial-port": ["acm:2341:805a", "acm:2341:005a"],
|
||||
"serial": "usb",
|
||||
"flash-1200-bps-reset": "true",
|
||||
"linkerscript": "targets/nano-33-ble.ld"
|
||||
}
|
||||
@@ -0,0 +1,14 @@
|
||||
|
||||
/*
|
||||
See also
|
||||
https://github.com/arduino/ArduinoCore-mbed/blob/master/variants/ARDUINO_NANO33BLE/linker_script.ld
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
FLASH_TEXT (rw) : ORIGIN = 0x10000, LENGTH = 0xf0000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000
|
||||
}
|
||||
|
||||
_stack_size = 4K;
|
||||
|
||||
INCLUDE "targets/arm.ld"
|
||||
@@ -0,0 +1,11 @@
|
||||
{
|
||||
"inherits": [
|
||||
"rp2040"
|
||||
],
|
||||
"serial": "uart",
|
||||
"build-tags": ["nano_rp2040"],
|
||||
"linkerscript": "targets/pico.ld",
|
||||
"extra-files": [
|
||||
"targets/pico-boot-stage2.S"
|
||||
]
|
||||
}
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["nrf52840"],
|
||||
"build-tags": ["nicenano","nrf52840_reset_uf2", "softdevice", "s140v6"],
|
||||
"serial": "usb",
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "NICENANO",
|
||||
|
||||
@@ -1,4 +1,5 @@
|
||||
{
|
||||
"inherits": ["esp8266"],
|
||||
"build-tags": ["nodemcu"]
|
||||
"build-tags": ["nodemcu"],
|
||||
"serial": "uart"
|
||||
}
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["nrf52840"],
|
||||
"build-tags": ["nrf52840_mdk_usb_dongle", "nrf52840_reset_uf2", "softdevice", "s140v6"],
|
||||
"serial": "usb",
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "MDK-DONGLE",
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["nrf52840"],
|
||||
"build-tags": ["nrf52840_mdk"],
|
||||
"serial": "usb",
|
||||
"flash-method": "openocd",
|
||||
"openocd-interface": "cmsis-dap"
|
||||
}
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["cortex-m3"],
|
||||
"build-tags": ["nucleof103rb", "stm32f103", "stm32f1","stm32"],
|
||||
"serial": "uart",
|
||||
"linkerscript": "targets/stm32f103rb.ld",
|
||||
"extra-files": [
|
||||
"src/device/stm32/stm32f103.s"
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["cortex-m7"],
|
||||
"build-tags": ["nucleof722ze", "stm32f7x2", "stm32f7", "stm32"],
|
||||
"serial": "uart",
|
||||
"linkerscript": "targets/stm32f7x2zetx.ld",
|
||||
"extra-files": [
|
||||
"src/device/stm32/stm32f7x2.s"
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["cortex-m0"],
|
||||
"build-tags": ["nucleol031k6", "stm32l031", "stm32l0x1", "stm32l0", "stm32"],
|
||||
"serial": "uart",
|
||||
"linkerscript": "targets/stm32l031k6.ld",
|
||||
"extra-files": [
|
||||
"src/device/stm32/stm32l0x1.s"
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["cortex-m4"],
|
||||
"build-tags": ["nucleol432kc", "stm32l432", "stm32l4x2", "stm32l4", "stm32"],
|
||||
"serial": "uart",
|
||||
"linkerscript": "targets/stm32l4x2.ld",
|
||||
"extra-files": [
|
||||
"src/device/stm32/stm32l4x2.s"
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["cortex-m33"],
|
||||
"build-tags": ["nucleol552ze", "stm32l552", "stm32l5x2", "stm32l5", "stm32"],
|
||||
"serial": "uart",
|
||||
"linkerscript": "targets/stm32l5x2xe.ld",
|
||||
"extra-files": [
|
||||
"src/device/stm32/stm32l552.s"
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["nrf52840"],
|
||||
"build-tags": ["particle_3rd_gen"],
|
||||
"serial": "uart",
|
||||
"flash-method": "openocd",
|
||||
"openocd-interface": "cmsis-dap"
|
||||
}
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["nrf51"],
|
||||
"build-tags": ["pca10031"],
|
||||
"serial": "uart",
|
||||
"flash-command": "nrfjprog -f nrf51 --sectorerase --program {hex} --reset",
|
||||
"openocd-interface": "cmsis-dap"
|
||||
}
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["nrf52"],
|
||||
"build-tags": ["pca10040"],
|
||||
"serial": "uart",
|
||||
"flash-method": "openocd",
|
||||
"flash-command": "nrfjprog -f nrf52 --sectorerase --program {hex} --reset",
|
||||
"openocd-interface": "jlink",
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["nrf52840"],
|
||||
"build-tags": ["pca10056"],
|
||||
"serial": "uart",
|
||||
"flash-method": "command",
|
||||
"flash-command": "nrfjprog -f nrf52 --sectorerase --program {hex} --reset",
|
||||
"msd-volume-name": "JLINK",
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["nrf52840"],
|
||||
"build-tags": ["pca10059"],
|
||||
"serial": "usb",
|
||||
"linkerscript": "targets/pca10059.ld",
|
||||
"flash-command": "nrfutil pkg generate --hw-version 52 --sd-req 0x0 --application {hex} --application-version 1 /tmp/tinygo_$$.zip && nrfutil dfu usb-serial -pkg /tmp/tinygo_$$.zip -p {port} -b 115200 && rm -f /tmp/tinygo_$$.zip"
|
||||
"binary-format": "nrf-dfu",
|
||||
"flash-command": "nrfutil dfu usb-serial -pkg {zip} -p {port} -b 115200"
|
||||
}
|
||||
|
||||
@@ -0,0 +1,17 @@
|
||||
// Raspberry Pi Pico Stage 2 Bootloader
|
||||
|
||||
//
|
||||
// This file defines the parameters specific to the flash-chip found
|
||||
// on the official Pico boards. The generic implementation is in
|
||||
// rp2040-boot-stage2.S
|
||||
//
|
||||
|
||||
#define BOARD_PICO_FLASH_SPI_CLKDIV 2
|
||||
#define BOARD_CMD_READ 0xeb
|
||||
#define BOARD_QUAD_OK 1
|
||||
#define BOARD_QUAD_ENABLE_STATUS_BYTE 2
|
||||
#define BOARD_QUAD_ENABLE_BIT_MASK 2
|
||||
#define BOARD_SPLIT_STATUS_WRITE 0
|
||||
#define BOARD_WAIT_CYCLES 4
|
||||
|
||||
#include "rp2040-boot-stage2.S"
|
||||
+2
-1
@@ -3,8 +3,9 @@
|
||||
"rp2040"
|
||||
],
|
||||
"build-tags": ["pico"],
|
||||
"serial": "uart",
|
||||
"linkerscript": "targets/pico.ld",
|
||||
"extra-files": [
|
||||
"targets/pico_boot_stage2.S"
|
||||
"targets/pico-boot-stage2.S"
|
||||
]
|
||||
}
|
||||
|
||||
+4
-25
@@ -1,31 +1,10 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH_TEXT (rx) : ORIGIN = 0x10000000, LENGTH = 2048k
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Second stage bootloader is prepended to the image. It must be 256 bytes big
|
||||
and checksummed. It is usually built by the boot_stage2 target
|
||||
in the Raspberry Pi Pico SDK
|
||||
*/
|
||||
|
||||
.boot2 : {
|
||||
__boot2_start__ = .;
|
||||
KEEP (*(.boot2))
|
||||
__boot2_end__ = .;
|
||||
} > FLASH_TEXT
|
||||
|
||||
ASSERT(__boot2_end__ - __boot2_start__ == 256,
|
||||
"ERROR: Pico second stage bootloader must be 256 bytes in size")
|
||||
|
||||
/* The second stage will always enter the image at the start of .text.
|
||||
The debugger will use the ELF entry point, which is the _entry_point
|
||||
symbol if present, otherwise defaults to start of .text.
|
||||
This can be used to transfer control back to the bootrom on debugger
|
||||
launches only, to perform proper flash setup.
|
||||
*/
|
||||
/* Reserve exactly 256 bytes at start of flash for second stage bootloader */
|
||||
BOOT2_TEXT (rx) : ORIGIN = 0x10000000, LENGTH = 256
|
||||
FLASH_TEXT (rx) : ORIGIN = 0x10000000 + 256, LENGTH = 2048K - 256
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256k
|
||||
}
|
||||
|
||||
INCLUDE "targets/rp2040.ld"
|
||||
|
||||
@@ -1,23 +0,0 @@
|
||||
// Padded and checksummed version of: /home/rkanchan/src/pico-sdk/build/src/rp2_common/boot_stage2/bs2_default.bin
|
||||
|
||||
.cpu cortex-m0plus
|
||||
.thumb
|
||||
|
||||
.section .boot2, "ax"
|
||||
|
||||
.byte 0x00, 0xb5, 0x32, 0x4b, 0x21, 0x20, 0x58, 0x60, 0x98, 0x68, 0x02, 0x21, 0x88, 0x43, 0x98, 0x60
|
||||
.byte 0xd8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x2e, 0x4b, 0x00, 0x21, 0x99, 0x60, 0x02, 0x21, 0x59, 0x61
|
||||
.byte 0x01, 0x21, 0xf0, 0x22, 0x99, 0x50, 0x2b, 0x49, 0x19, 0x60, 0x01, 0x21, 0x99, 0x60, 0x35, 0x20
|
||||
.byte 0x00, 0xf0, 0x44, 0xf8, 0x02, 0x22, 0x90, 0x42, 0x14, 0xd0, 0x06, 0x21, 0x19, 0x66, 0x00, 0xf0
|
||||
.byte 0x34, 0xf8, 0x19, 0x6e, 0x01, 0x21, 0x19, 0x66, 0x00, 0x20, 0x18, 0x66, 0x1a, 0x66, 0x00, 0xf0
|
||||
.byte 0x2c, 0xf8, 0x19, 0x6e, 0x19, 0x6e, 0x19, 0x6e, 0x05, 0x20, 0x00, 0xf0, 0x2f, 0xf8, 0x01, 0x21
|
||||
.byte 0x08, 0x42, 0xf9, 0xd1, 0x00, 0x21, 0x99, 0x60, 0x1b, 0x49, 0x19, 0x60, 0x00, 0x21, 0x59, 0x60
|
||||
.byte 0x1a, 0x49, 0x1b, 0x48, 0x01, 0x60, 0x01, 0x21, 0x99, 0x60, 0xeb, 0x21, 0x19, 0x66, 0xa0, 0x21
|
||||
.byte 0x19, 0x66, 0x00, 0xf0, 0x12, 0xf8, 0x00, 0x21, 0x99, 0x60, 0x16, 0x49, 0x14, 0x48, 0x01, 0x60
|
||||
.byte 0x01, 0x21, 0x99, 0x60, 0x01, 0xbc, 0x00, 0x28, 0x00, 0xd0, 0x00, 0x47, 0x12, 0x48, 0x13, 0x49
|
||||
.byte 0x08, 0x60, 0x03, 0xc8, 0x80, 0xf3, 0x08, 0x88, 0x08, 0x47, 0x03, 0xb5, 0x99, 0x6a, 0x04, 0x20
|
||||
.byte 0x01, 0x42, 0xfb, 0xd0, 0x01, 0x20, 0x01, 0x42, 0xf8, 0xd1, 0x03, 0xbd, 0x02, 0xb5, 0x18, 0x66
|
||||
.byte 0x18, 0x66, 0xff, 0xf7, 0xf2, 0xff, 0x18, 0x6e, 0x18, 0x6e, 0x02, 0xbd, 0x00, 0x00, 0x02, 0x40
|
||||
.byte 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0x00, 0x00, 0x03, 0x5f, 0x00, 0x21, 0x22, 0x00, 0x00
|
||||
.byte 0xf4, 0x00, 0x00, 0x18, 0x22, 0x20, 0x00, 0xa0, 0x00, 0x01, 0x00, 0x10, 0x08, 0xed, 0x00, 0xe0
|
||||
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x74, 0xb2, 0x4e, 0x7a
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["nrf52"],
|
||||
"build-tags": ["pinetime_devkit0"],
|
||||
"serial": "uart",
|
||||
"flash-method": "openocd",
|
||||
"flash-command": "nrfjprog -f nrf52 --sectorerase --program {hex} --reset",
|
||||
"openocd-interface": "jlink",
|
||||
|
||||
@@ -1,8 +1,10 @@
|
||||
{
|
||||
"inherits": ["atsamd51j19a"],
|
||||
"build-tags": ["pybadge"],
|
||||
"serial": "usb",
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"serial-port": ["acm:239a:8033", "acm:239a:33"],
|
||||
"msd-volume-name": "PYBADGEBOOT",
|
||||
"msd-firmware-name": "arcade.uf2"
|
||||
}
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["atsamd51j19a"],
|
||||
"build-tags": ["pygamer"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:239a:803d", "acm:239a:003d", "acm:239a:803e"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "PYGAMERBOOT",
|
||||
|
||||
@@ -1,8 +1,10 @@
|
||||
{
|
||||
"inherits": ["atsamd51j20a"],
|
||||
"build-tags": ["pyportal"],
|
||||
"serial": "usb",
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"serial-port": ["acm:239a:8035", "acm:239a:35", "acm:239a:8036"],
|
||||
"msd-volume-name": "PORTALBOOT",
|
||||
"msd-firmware-name": "firmware.uf2"
|
||||
}
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["atsamd21e18a"],
|
||||
"build-tags": ["qtpy"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:239a:80cb", "acm:239a:00cb", "acm:239a:00cc"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "QTPY_BOOT",
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["nrf52840"],
|
||||
"build-tags": ["reelboard"],
|
||||
"serial": "uart",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "reel-board",
|
||||
"msd-firmware-name": "firmware.hex",
|
||||
|
||||
@@ -0,0 +1,471 @@
|
||||
//
|
||||
// Implementation of RP2040 stage 2 boot loader. This code is derived from the
|
||||
// Winbond W25Q080 implementation (as found in the Pico) in the official Pico SDK.
|
||||
//
|
||||
// This implementation has been made 'stand-alone' by including necessary code /
|
||||
// symbols from the included files in the reference implementation directly into
|
||||
// the source. It has also been modified to include the conditional logic from
|
||||
// the CircuitPython implementation that supports additional flash chips. The
|
||||
// CiruitPython source is here:
|
||||
// https://github.com/adafruit/circuitpython/blob/main/ports/raspberrypi/stage2.c.jinja
|
||||
//
|
||||
// This file cannot be assembled directly, instead assemble the board-specific file
|
||||
// (such as pico-boot-stage2.S) which defines the parameters specific to the flash
|
||||
// chip included on that board.
|
||||
//
|
||||
// Care has been taken to preserve ordering and it has been verified the generated
|
||||
// binary is byte-for-byte identical to the reference code binary when assembled for
|
||||
// the Pico.
|
||||
//
|
||||
// Note: the stage 2 boot loader must be 256 bytes in length and have a checksum
|
||||
// present. In TinyGo, the linker script is responsible for allocating 256 bytes
|
||||
// for the .boot2 section and the build logic patches the checksum into the
|
||||
// binary after linking, controlled by the '<target>.json' flag 'rp2040-boot-patch'.
|
||||
//
|
||||
// The stage 2 bootstrap section can be inspected in an elf file using this command:
|
||||
// objdump -s -j .boot2 <binary>.elf
|
||||
//
|
||||
// Original Source:
|
||||
// https://github.com/raspberrypi/pico-sdk/blob/master/src/rp2_common/boot_stage2/boot2_w25q080.S
|
||||
//
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Second stage boot code
|
||||
// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
//
|
||||
// Device: Winbond W25Q080
|
||||
// Also supports W25Q16JV (which has some different SR instructions)
|
||||
// Also supports AT25SF081
|
||||
// Also supports S25FL132K0
|
||||
//
|
||||
// Description: Configures W25Q080 to run in Quad I/O continuous read XIP mode
|
||||
//
|
||||
// Details: * Check status register 2 to determine if QSPI mode is enabled,
|
||||
// and perform an SR2 programming cycle if necessary.
|
||||
// * Use SSI to perform a dummy 0xEB read command, with the mode
|
||||
// continuation bits set, so that the flash will not require
|
||||
// 0xEB instruction prefix on subsequent reads.
|
||||
// * Configure SSI to write address, mode bits, but no instruction.
|
||||
// SSI + flash are now jointly in a state where continuous reads
|
||||
// can take place.
|
||||
// * Jump to exit pointer passed in via lr. Bootrom passes null,
|
||||
// in which case this code uses a default 256 byte flash offset
|
||||
//
|
||||
// Building: * This code must be position-independent, and use stack only
|
||||
// * The code will be padded to a size of 256 bytes, including a
|
||||
// 4-byte checksum. Therefore code size cannot exceed 252 bytes.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
|
||||
//
|
||||
// Expanded include files
|
||||
//
|
||||
#define CMD_WRITE_ENABLE 0x06
|
||||
#define CMD_READ_STATUS 0x05
|
||||
#define CMD_READ_STATUS2 0x35
|
||||
#define CMD_WRITE_STATUS1 0x01
|
||||
#define CMD_WRITE_STATUS2 0x31
|
||||
#define SREG_DATA 0x02 // Enable quad-SPI mode
|
||||
|
||||
#define XIP_BASE 0x10000000
|
||||
#define XIP_SSI_BASE 0x18000000
|
||||
#define PADS_QSPI_BASE 0x40020000
|
||||
#define PPB_BASE 0xe0000000
|
||||
|
||||
#define M0PLUS_VTOR_OFFSET 0x0000ed08
|
||||
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB 4
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS 0x00000001
|
||||
#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET 0x00000004
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET 0x00000008
|
||||
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS 0x00000002
|
||||
#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET 0x0000000c
|
||||
#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET 0x00000010
|
||||
#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET 0x00000014
|
||||
|
||||
#define SSI_CTRLR0_OFFSET 0x00000000
|
||||
#define SSI_CTRLR1_OFFSET 0x00000004
|
||||
#define SSI_SSIENR_OFFSET 0x00000008
|
||||
#define SSI_BAUDR_OFFSET 0x00000014
|
||||
#define SSI_SR_OFFSET 0x00000028
|
||||
#define SSI_DR0_OFFSET 0x00000060
|
||||
#define SSI_RX_SAMPLE_DLY_OFFSET 0x000000f0
|
||||
|
||||
#define SSI_CTRLR0_DFS_32_LSB 16
|
||||
|
||||
#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD 0x2
|
||||
#define SSI_CTRLR0_SPI_FRF_LSB 21
|
||||
|
||||
#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX 0x0
|
||||
#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ 0x3
|
||||
#define SSI_CTRLR0_TMOD_LSB 8
|
||||
|
||||
#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A 0x1
|
||||
#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A 0x2
|
||||
|
||||
#define SSI_SPI_CTRLR0_OFFSET 0x000000f4
|
||||
|
||||
#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE 0x0
|
||||
#define SSI_SPI_CTRLR0_INST_L_VALUE_8B 0x2
|
||||
|
||||
#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB 0
|
||||
#define SSI_SPI_CTRLR0_ADDR_L_LSB 2
|
||||
#define SSI_SPI_CTRLR0_INST_L_LSB 8
|
||||
#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB 11
|
||||
#define SSI_SPI_CTRLR0_XIP_CMD_LSB 24
|
||||
|
||||
#define SSI_SR_BUSY_BITS 0x00000001
|
||||
#define SSI_SR_TFE_BITS 0x00000004
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Config section
|
||||
// ----------------------------------------------------------------------------
|
||||
// It should be possible to support most flash devices by modifying this section
|
||||
|
||||
// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
|
||||
// This must be a positive, even integer.
|
||||
// The bootrom is very conservative with SPI frequency, but here we should be
|
||||
// as aggressive as possible.
|
||||
|
||||
#define PICO_FLASH_SPI_CLKDIV BOARD_PICO_FLASH_SPI_CLKDIV
|
||||
#if PICO_FLASH_SPI_CLKDIV & 1
|
||||
#error PICO_FLASH_SPI_CLKDIV must be even
|
||||
#endif
|
||||
|
||||
#if BOARD_QUAD_OK==1
|
||||
// Define interface width: single/dual/quad IO
|
||||
#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
|
||||
#define TRANSACTION_TYPE SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A
|
||||
// Note that the INST_L field is used to select what XIP data gets pushed into
|
||||
// the TX FIFO:
|
||||
// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD
|
||||
// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD
|
||||
#define INSTRUCTION_LENGTH SSI_SPI_CTRLR0_INST_L_VALUE_NONE
|
||||
#define READ_INSTRUCTION MODE_CONTINUOUS_READ
|
||||
#define ADDR_L 8 // 6 for address, 2 for mode
|
||||
#else
|
||||
#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_STD
|
||||
#define TRANSACTION_TYPE SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A
|
||||
#define INSTRUCTION_LENGTH SSI_SPI_CTRLR0_INST_L_VALUE_8B
|
||||
#define READ_INSTRUCTION BOARD_CMD_READ
|
||||
#define ADDR_L 6 // * 4 = 24
|
||||
#endif
|
||||
|
||||
// The flash-chip specific read isntruction
|
||||
#define CMD_READ BOARD_CMD_READ
|
||||
|
||||
// "Mode bits" are 8 special bits sent immediately after
|
||||
// the address bits in a "Read Data Fast Quad I/O" command sequence.
|
||||
// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
|
||||
// next read does not require the 0xeb instruction prefix.
|
||||
#define MODE_CONTINUOUS_READ 0xa0
|
||||
|
||||
// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles
|
||||
// are required.
|
||||
#define WAIT_CYCLES BOARD_WAIT_CYCLES
|
||||
|
||||
|
||||
// If defined, we will read status reg, compare to SREG_DATA, and overwrite
|
||||
// with our value if the SR doesn't match.
|
||||
// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to
|
||||
// SR2 (31h cmd) as the latter command isn't supported by WX25Q080.
|
||||
// This isn't great because it will remove block protections.
|
||||
// A better solution is to use a volatile SR write if your device supports it.
|
||||
#define PROGRAM_STATUS_REG
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m0plus
|
||||
.thumb
|
||||
.section .boot2, "ax"
|
||||
|
||||
// The exit point is passed in lr. If entered from bootrom, this will be the
|
||||
// flash address immediately following this second stage (0x10000100).
|
||||
// Otherwise it will be a return address -- second stage being called as a
|
||||
// function by user code, after copying out of XIP region. r3 holds SSI base,
|
||||
// r0...2 used as temporaries. Other GPRs not used.
|
||||
.global _stage2_boot
|
||||
.type _stage2_boot,%function
|
||||
.thumb_func
|
||||
_stage2_boot:
|
||||
push {lr}
|
||||
|
||||
// Set pad configuration:
|
||||
// - SCLK 8mA drive, no slew limiting
|
||||
// - SDx disable input Schmitt to reduce delay
|
||||
|
||||
ldr r3, =PADS_QSPI_BASE
|
||||
movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS)
|
||||
str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
|
||||
ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
|
||||
movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS
|
||||
bics r0, r1
|
||||
#if BOARD_QUAD_OK==1
|
||||
str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
|
||||
#endif
|
||||
str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
|
||||
#if BOARD_QUAD_OK==1
|
||||
str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
|
||||
str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET]
|
||||
#endif
|
||||
|
||||
ldr r3, =XIP_SSI_BASE
|
||||
|
||||
// Disable SSI to allow further config
|
||||
movs r1, #0
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
|
||||
// Set baud rate
|
||||
movs r1, #PICO_FLASH_SPI_CLKDIV
|
||||
str r1, [r3, #SSI_BAUDR_OFFSET]
|
||||
|
||||
// Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means,
|
||||
// if the flash launches data on SCLK posedge, we capture it at the time that
|
||||
// the next SCLK posedge is launched. This is shortly before that posedge
|
||||
// arrives at the flash, so data hold time should be ok. For
|
||||
// PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect.
|
||||
|
||||
movs r1, #1
|
||||
movs r2, #SSI_RX_SAMPLE_DLY_OFFSET // == 0xf0 so need 8 bits of offset significance
|
||||
str r1, [r3, r2]
|
||||
|
||||
// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
|
||||
// (i.e. turn WPn and HOLDn into IO2/IO3)
|
||||
#ifdef PROGRAM_STATUS_REG
|
||||
program_sregs:
|
||||
#define CTRL0_SPI_TXRX \
|
||||
(7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \
|
||||
(SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB)
|
||||
|
||||
ldr r1, =(CTRL0_SPI_TXRX)
|
||||
str r1, [r3, #SSI_CTRLR0_OFFSET]
|
||||
|
||||
// Enable SSI and select slave 0
|
||||
movs r1, #1
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
|
||||
// Check whether SR needs updating
|
||||
#if BOARD_QUAD_OK==1
|
||||
# if BOARD_QUAD_ENABLE_STATUS_BYTE==1
|
||||
movs r0, #CMD_READ_STATUS1
|
||||
# elif BOARD_QUAD_ENABLE_STATUS_BYTE==2
|
||||
movs r0, #CMD_READ_STATUS2
|
||||
# endif
|
||||
|
||||
bl read_flash_sreg
|
||||
movs r2, #BOARD_QUAD_ENABLE_BIT_MASK
|
||||
cmp r0, r2
|
||||
beq skip_sreg_programming
|
||||
|
||||
// Send write enable command
|
||||
movs r1, #CMD_WRITE_ENABLE
|
||||
str r1, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
// Poll for completion and discard RX
|
||||
bl wait_ssi_ready
|
||||
ldr r1, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
// Send status write command followed by data bytes
|
||||
# if BOARD_SPLIT_STATUS_WRITE==1
|
||||
# if BOARD_QUAD_ENABLE_STATUS_BYTE==1
|
||||
movs r1, #CMD_WRITE_STATUS1
|
||||
# elif BOARD_QUAD_ENABLE_STATUS_BYTE==2
|
||||
movs r1, #CMD_WRITE_STATUS2
|
||||
# endif
|
||||
str r1, [r3, #SSI_DR0_OFFSET]
|
||||
str r2, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
bl wait_ssi_ready
|
||||
//ldr r1, [r3, #SSI_DR0_OFFSET]
|
||||
ldr r1, [r3, #SSI_DR0_OFFSET]
|
||||
ldr r1, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
# else
|
||||
movs r1, #CMD_WRITE_STATUS1
|
||||
str r1, [r3, #SSI_DR0_OFFSET]
|
||||
# if BOARD_QUAD_ENABLE_STATUS_BYTE==2
|
||||
movs r0, #0
|
||||
str r0, [r3, #SSI_DR0_OFFSET]
|
||||
# endif
|
||||
str r2, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
bl wait_ssi_ready
|
||||
ldr r1, [r3, #SSI_DR0_OFFSET]
|
||||
ldr r1, [r3, #SSI_DR0_OFFSET]
|
||||
# if BOARD_QUAD_ENABLE_STATUS_BYTE==2
|
||||
ldr r1, [r3, #SSI_DR0_OFFSET]
|
||||
# endif
|
||||
|
||||
# endif
|
||||
// Poll status register for write completion
|
||||
1:
|
||||
movs r0, #CMD_READ_STATUS
|
||||
bl read_flash_sreg
|
||||
movs r1, #1
|
||||
tst r0, r1
|
||||
bne 1b
|
||||
#endif
|
||||
|
||||
skip_sreg_programming:
|
||||
|
||||
// Disable SSI again so that it can be reconfigured
|
||||
movs r1, #0
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
#endif
|
||||
|
||||
// Currently the flash expects an 8 bit serial command prefix on every
|
||||
// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O
|
||||
// command, with mode bits set such that the flash will not expect a serial
|
||||
// command prefix on *subsequent* transfers. We don't care about the results
|
||||
// of the read, the important part is the mode bits.
|
||||
|
||||
dummy_read:
|
||||
#define CTRLR0_ENTER_XIP \
|
||||
(FRAME_FORMAT /* Quad I/O mode */ \
|
||||
<< SSI_CTRLR0_SPI_FRF_LSB) | \
|
||||
(31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \
|
||||
(SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \
|
||||
<< SSI_CTRLR0_TMOD_LSB)
|
||||
|
||||
ldr r1, =(CTRLR0_ENTER_XIP)
|
||||
str r1, [r3, #SSI_CTRLR0_OFFSET]
|
||||
|
||||
movs r1, #0x0 // NDF=0 (single 32b read)
|
||||
str r1, [r3, #SSI_CTRLR1_OFFSET]
|
||||
|
||||
#if BOARD_QUAD_OK==1
|
||||
#define SPI_CTRLR0_ENTER_XIP \
|
||||
(ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \
|
||||
(WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
|
||||
(SSI_SPI_CTRLR0_INST_L_VALUE_8B \
|
||||
<< SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \
|
||||
(SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \
|
||||
<< SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
|
||||
|
||||
ldr r1, =(SPI_CTRLR0_ENTER_XIP)
|
||||
ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
|
||||
str r1, [r0]
|
||||
|
||||
movs r1, #1 // Re-enable SSI
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET]
|
||||
|
||||
movs r1, #CMD_READ
|
||||
str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
|
||||
movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
|
||||
str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
|
||||
|
||||
// Poll for completion
|
||||
bl wait_ssi_ready
|
||||
|
||||
// The flash is in a state where we can blast addresses in parallel, and get
|
||||
// parallel data back. Now configure the SSI to translate XIP bus accesses
|
||||
// into QSPI transfers of this form.
|
||||
|
||||
movs r1, #0
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config
|
||||
#endif
|
||||
|
||||
// Note that the INST_L field is used to select what XIP data gets pushed into
|
||||
// the TX FIFO:
|
||||
// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD
|
||||
// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD
|
||||
configure_ssi:
|
||||
#define SPI_CTRLR0_XIP \
|
||||
(READ_INSTRUCTION /* Mode bits to keep flash in continuous read mode */ \
|
||||
<< SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
|
||||
(ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \
|
||||
(WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
|
||||
(INSTRUCTION_LENGTH /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
|
||||
<< SSI_SPI_CTRLR0_INST_L_LSB) | \
|
||||
(TRANSACTION_TYPE /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \
|
||||
<< SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
|
||||
|
||||
ldr r1, =(SPI_CTRLR0_XIP)
|
||||
|
||||
ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
|
||||
str r1, [r0]
|
||||
|
||||
movs r1, #1
|
||||
str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI
|
||||
|
||||
// Bus accesses to the XIP window will now be transparently serviced by the
|
||||
// external flash on cache miss. We are ready to run code from flash.
|
||||
|
||||
|
||||
//
|
||||
// Helper Includes
|
||||
//
|
||||
|
||||
//
|
||||
// #include "boot2_helpers/exit_from_boot2.S"
|
||||
//
|
||||
|
||||
// If entered from the bootrom, lr (which we earlier pushed) will be 0,
|
||||
// and we vector through the table at the start of the main flash image.
|
||||
// Any regular function call will have a nonzero value for lr.
|
||||
check_return:
|
||||
pop {r0}
|
||||
cmp r0, #0
|
||||
beq vector_into_flash
|
||||
bx r0
|
||||
vector_into_flash:
|
||||
ldr r0, =(XIP_BASE + 0x100)
|
||||
ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET)
|
||||
str r0, [r1]
|
||||
ldmia r0, {r0, r1}
|
||||
msr msp, r0
|
||||
bx r1
|
||||
|
||||
//
|
||||
// #include "boot2_helpers/wait_ssi_ready.S"
|
||||
//
|
||||
wait_ssi_ready:
|
||||
push {r0, r1, lr}
|
||||
|
||||
// Command is complete when there is nothing left to send
|
||||
// (TX FIFO empty) and SSI is no longer busy (CSn deasserted)
|
||||
1:
|
||||
ldr r1, [r3, #SSI_SR_OFFSET]
|
||||
movs r0, #SSI_SR_TFE_BITS
|
||||
tst r1, r0
|
||||
beq 1b
|
||||
movs r0, #SSI_SR_BUSY_BITS
|
||||
tst r1, r0
|
||||
bne 1b
|
||||
|
||||
pop {r0, r1, pc}
|
||||
|
||||
|
||||
#ifdef PROGRAM_STATUS_REG
|
||||
|
||||
//
|
||||
// #include "boot2_helpers/read_flash_sreg.S"
|
||||
//
|
||||
|
||||
// Pass status read cmd into r0.
|
||||
// Returns status value in r0.
|
||||
.global read_flash_sreg
|
||||
.type read_flash_sreg,%function
|
||||
.thumb_func
|
||||
read_flash_sreg:
|
||||
push {r1, lr}
|
||||
str r0, [r3, #SSI_DR0_OFFSET]
|
||||
// Dummy byte:
|
||||
str r0, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
bl wait_ssi_ready
|
||||
// Discard first byte and combine the next two
|
||||
ldr r0, [r3, #SSI_DR0_OFFSET]
|
||||
ldr r0, [r3, #SSI_DR0_OFFSET]
|
||||
|
||||
pop {r1, pc}
|
||||
|
||||
#endif
|
||||
|
||||
.global literals
|
||||
literals:
|
||||
.ltorg
|
||||
|
||||
.end
|
||||
@@ -6,6 +6,7 @@
|
||||
"msd-firmware-name": "firmware.uf2",
|
||||
"binary-format": "uf2",
|
||||
"uf2-family-id": "0xe48bff56",
|
||||
"rp2040-boot-patch": true,
|
||||
"extra-files": [
|
||||
"src/device/rp/rp2040.s"
|
||||
]
|
||||
|
||||
+25
-5
@@ -1,9 +1,29 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256k
|
||||
}
|
||||
|
||||
_stack_size = 2K;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Second stage bootloader is prepended to the image. It must be 256 bytes
|
||||
and checksummed. The gap to the checksum is zero-padded.
|
||||
*/
|
||||
.boot2 : {
|
||||
__boot2_start__ = .;
|
||||
KEEP (*(.boot2));
|
||||
|
||||
/* Explicitly allocate space for CRC32 checksum at end of second stage
|
||||
bootloader
|
||||
*/
|
||||
. = __boot2_start__ + 256 - 4;
|
||||
LONG(0)
|
||||
} > BOOT2_TEXT = 0x0
|
||||
|
||||
/* The second stage will always enter the image at the start of .text.
|
||||
The debugger will use the ELF entry point, which is the _entry_point
|
||||
symbol if present, otherwise defaults to start of .text.
|
||||
This can be used to transfer control back to the bootrom on debugger
|
||||
launches only, to perform proper flash setup.
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "targets/arm.ld"
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["cortex-m4"],
|
||||
"build-tags": ["stm32f4disco", "stm32f407", "stm32f4", "stm32"],
|
||||
"serial": "uart",
|
||||
"linkerscript": "targets/stm32f407.ld",
|
||||
"extra-files": [
|
||||
"src/device/stm32/stm32f407.s"
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["cortex-m4"],
|
||||
"build-tags": ["teensy36", "teensy", "mk66f18", "nxp"],
|
||||
"serial": "uart",
|
||||
"linkerscript": "targets/nxpmk66f18.ld",
|
||||
"extra-files": [
|
||||
"src/device/nxp/mk66f18.s",
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["cortex-m7"],
|
||||
"build-tags": ["teensy40", "teensy", "mimxrt1062", "nxp"],
|
||||
"serial": "uart",
|
||||
"automatic-stack-size": false,
|
||||
"default-stack-size": 4096,
|
||||
"linkerscript": "targets/mimxrt1062-teensy40.ld",
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["atsamd21e18a"],
|
||||
"build-tags": ["trinket_m0"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:239a:801e", "acm:239a:001e"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "TRINKETBOOT",
|
||||
|
||||
+1
-1
@@ -1,6 +1,6 @@
|
||||
{
|
||||
"llvm-target": "wasm32--wasi",
|
||||
"build-tags": ["wasm", "wasi"],
|
||||
"build-tags": ["tinygo.wasm", "wasi"],
|
||||
"goos": "linux",
|
||||
"goarch": "arm",
|
||||
"linker": "wasm-ld",
|
||||
|
||||
+1
-1
@@ -1,6 +1,6 @@
|
||||
{
|
||||
"llvm-target": "wasm32--wasi",
|
||||
"build-tags": ["js", "wasm"],
|
||||
"build-tags": ["tinygo.wasm"],
|
||||
"goos": "js",
|
||||
"goarch": "wasm",
|
||||
"linker": "wasm-ld",
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["atsamd51p19a"],
|
||||
"build-tags": ["wioterminal"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:2886:002d", "acm:2886:802d"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "Arduino",
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
{
|
||||
"inherits": ["nrf52"],
|
||||
"build-tags": ["x9pro"],
|
||||
"serial": "uart",
|
||||
"flash-method": "openocd",
|
||||
"flash-command": "nrfjprog -f nrf52 --sectorerase --program {hex} --reset",
|
||||
"openocd-interface": "jlink",
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
{
|
||||
"inherits": ["atsamd21g18a"],
|
||||
"build-tags": ["xiao"],
|
||||
"serial": "usb",
|
||||
"serial-port": ["acm:2886:802f", "acm:2886:002f"],
|
||||
"flash-1200-bps-reset": "true",
|
||||
"flash-method": "msd",
|
||||
"msd-volume-name": "Arduino",
|
||||
|
||||
Reference in New Issue
Block a user