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machine/esp32c6: add ADC driver
Adds machine_esp32c6_adc.go implementing the machine.ADC interface for ESP32-C6 (ADC1 only, GPIO0–GPIO6, channels 0–6; there is no ADC2). Signed-off-by: deadprogram <ron@hybridgroup.com>
This commit is contained in:
deadprogram
Ayke
@@ -0,0 +1,392 @@
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//go:build esp32c6
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package machine
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import (
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"device/esp"
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"errors"
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"runtime/volatile"
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"unsafe"
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)
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// newRegI2C returns the regI2C configured for ESP32-C6: hostID=0, drefInit=1.
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// I2C_SAR_ADC_HOSTID = 0 per soc/esp32c6/include/soc/regi2c_saradc.h.
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func newRegI2C() regI2C { return regI2C{hostID: 0, drefInit: 1} }
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const (
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// ADC attenuation values for ESP32-C6 APB_SARADC.
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// 0 dB : ~0 .. 1.1 V
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// 11 dB : ~0 .. 3.3 V (matches typical VDD)
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atten0dB = 0
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atten11dB = 3
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)
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// InitADC initialises the APB_SARADC peripheral on ESP32-C6.
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// On C6 the clock/reset gating moved to PCR (not SYSTEM as on C3), and the
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// SARADC CLKM divider configuration also lives in PCR.
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func InitADC() {
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// Reset and enable the SARADC bus clock via PCR.
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esp.PCR.SetSARADC_CONF_SARADC_RST_EN(1)
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esp.PCR.SetSARADC_CONF_SARADC_CLK_EN(1)
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esp.PCR.SetSARADC_CONF_SARADC_RST_EN(0)
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// Select clock source 2 (PLL_F80M), divider = 1, no fractional.
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esp.PCR.SetSARADC_CLKM_CONF_SARADC_CLKM_SEL(2)
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esp.PCR.SetSARADC_CLKM_CONF_SARADC_CLKM_DIV_NUM(1)
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esp.PCR.SetSARADC_CLKM_CONF_SARADC_CLKM_DIV_B(0)
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esp.PCR.SetSARADC_CLKM_CONF_SARADC_CLKM_DIV_A(0)
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esp.PCR.SetSARADC_CLKM_CONF_SARADC_CLKM_EN(1)
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// Power up the SAR ADC and configure FSM timing (same register layout as C3).
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esp.APB_SARADC.SetCTRL_SARADC_XPD_SAR_FORCE(1)
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esp.APB_SARADC.SetFSM_WAIT_SARADC_XPD_WAIT(8)
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esp.APB_SARADC.SetFSM_WAIT_SARADC_RSTB_WAIT(8)
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esp.APB_SARADC.SetFSM_WAIT_SARADC_STANDBY_WAIT(100)
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adcSelfCalibrate()
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}
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// ESP32-C6 ADC pin mapping: ADC1 = GPIO0–GPIO6 (ch 0–6). There is no ADC2.
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// (The machine_esp32c6.go file defines ADC0..ADC6 as GPIO0..GPIO6.)
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func (a ADC) Configure(config ADCConfig) error {
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if a.Pin > 6 {
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return errors.New("invalid ADC pin for ESP32-C6")
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}
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a.Pin.Configure(PinConfig{Mode: PinAnalog})
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return nil
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}
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// Get performs a single ADC1 conversion and returns a 16-bit value.
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// The raw 12-bit result (0..4095) is left-shifted by 4 to fill 16 bits.
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func (a ADC) Get() uint16 {
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if a.Pin > 6 {
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return 0
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}
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esp.APB_SARADC.SetONETIME_SAMPLE_SARADC_ONETIME_ATTEN(atten11dB)
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esp.APB_SARADC.SetINT_CLR_APB_SARADC1_DONE_INT_CLR(1)
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esp.APB_SARADC.SetONETIME_SAMPLE_SARADC_ONETIME_START(0)
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esp.APB_SARADC.SetONETIME_SAMPLE_SARADC_ONETIME_CHANNEL(uint32(a.Pin))
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esp.APB_SARADC.SetONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE(1)
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esp.APB_SARADC.SetONETIME_SAMPLE_SARADC_ONETIME_START(1)
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for esp.APB_SARADC.GetINT_RAW_APB_SARADC1_DONE_INT_RAW() == 0 {
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}
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raw := esp.APB_SARADC.GetSAR1DATA_STATUS_APB_SARADC1_DATA()
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esp.APB_SARADC.SetONETIME_SAMPLE_SARADC_ONETIME_START(0)
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esp.APB_SARADC.SetONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE(0)
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return uint16(raw&0xfff) << 4
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}
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// ── regI2C: internal I2C-bus (LP_I2C_ANA_MST) for SAR ADC calibration ───────
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//
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// On ESP32-C6 the "REGI2C" master moved from the embedded SENS/APB_SARADC
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// controller (0x6000_E000) used on C3/S3 to the dedicated LP_I2C_ANA_MST
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// peripheral at 0x600b_2400. The SAR ADC block address and register layout
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// (DREF, ENCAL_GND, INIT_CODE) remain identical to C3.
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//
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// LP_I2C_ANA_MST.I2C0_CTRL bit layout (25-bit command field):
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// [7:0] = slave block address (0x69 for I2C_SAR_ADC)
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// [15:8] = register address within the block
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// [23:16]= write data (8 bits)
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// [24] = WR_CNTL: 0=read, 1=write
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// [25] = BUSY (read-only, set by hardware while processing)
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//
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// Source: components/esp_rom/patches/esp_rom_regi2c_esp32c6.c in esp-idf
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// regI2C wraps the internal I2C bus used for SAR ADC calibration registers.
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// Fields hold chip-specific parameters.
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type regI2C struct {
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// hostID is the I2C_SAR_ADC_HOSTID (0 for ESP32-C6, matching regi2c_saradc.h).
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hostID uint8
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// drefInit is the DREF reference value written during calibrationInit (1 for C6).
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drefInit uint8
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}
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// SAR ADC I2C register layout — identical to ESP32-C3 / ESP32-S3.
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// Source: soc/esp32c6/include/soc/regi2c_saradc.h
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const (
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i2cSarADC = uint8(0x69)
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adc1DrefAddr = uint8(0x2)
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adc1DrefMSB = uint8(6)
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adc1DrefLSB = uint8(4)
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adc2DrefAddr = uint8(0x5)
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adc2DrefMSB = uint8(6)
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adc2DrefLSB = uint8(4)
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adc1EncalGndAddr = uint8(0x7)
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adc1EncalGndMSB = uint8(5)
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adc1EncalGndLSB = uint8(5)
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adc2EncalGndAddr = uint8(0x7)
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adc2EncalGndMSB = uint8(7)
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adc2EncalGndLSB = uint8(7)
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adc1InitCodeHighAddr = uint8(0x1)
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adc1InitCodeHighMSB = uint8(3)
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adc1InitCodeHighLSB = uint8(0)
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adc1InitCodeLowAddr = uint8(0x0)
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adc1InitCodeLowMSB = uint8(7)
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adc1InitCodeLowLSB = uint8(0)
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adc2InitCodeHighAddr = uint8(0x4)
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adc2InitCodeHighMSB = uint8(3)
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adc2InitCodeHighLSB = uint8(0)
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adc2InitCodeLowAddr = uint8(0x3)
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adc2InitCodeLowMSB = uint8(7)
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adc2InitCodeLowLSB = uint8(0)
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// adcCalOffsetRange is the binary search upper bound (12-bit full scale).
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adcCalOffsetRange = uint32(4096)
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// adcCalMaxIterations caps binary search iterations.
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adcCalMaxIterations = 16
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)
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// LP_I2C_ANA_MST I2C0_CTRL bit-field shifts (see file header comment).
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const (
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c6SlaveIDShift = 0 // bits [7:0]
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c6AddrShift = 8 // bits [15:8]
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c6DataShift = 16 // bits [23:16]
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c6WrCntlShift = 24 // bit [24]
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c6BusyBit = uint32(1 << 25)
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// c6SarI2CDeviceEn is BIT(7) in LP_I2C_ANA_MST.DEVICE_EN for I2C_SAR_ADC (0x69).
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c6SarI2CDeviceEn = uint32(1 << 7)
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)
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// ANA_CONFIG / ANA_CONFIG2 register addresses and bits for the internal SAR I2C
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// domain on ESP32-C6. These differ from C3's SENS block (0x6000_E044/048).
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// Source: soc/esp32c6/include/soc/regi2c_defs.h
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const (
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c6AnaConfigReg = uintptr(0x600AF81C) // clear ANA_I2C_SAR_FORCE_PD (bit 18)
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c6AnaConfig2Reg = uintptr(0x600AF820) // set ANA_I2C_SAR_FORCE_PU (bit 16)
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c6SarForcePD = uint32(1 << 18)
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c6SarForcePU = uint32(1 << 16)
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)
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// sarEnable powers up the internal SAR I2C domain and enables the LP_I2C_ANA_MST
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// clock and SAR slave device before any regI2C access.
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// Matches regi2c_ctrl_ll_i2c_saradc_enable() + regi2c_enable_block(REGI2C_SAR_I2C).
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func (r regI2C) sarEnable() {
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cfg := (*volatile.Register32)(unsafe.Pointer(c6AnaConfigReg))
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cfg2 := (*volatile.Register32)(unsafe.Pointer(c6AnaConfig2Reg))
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cfg.Set(cfg.Get() &^ c6SarForcePD)
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cfg2.Set(cfg2.Get() | c6SarForcePU)
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// Enable the LP_I2C_ANA_MST master clock (MODEM_LPCON.CLK_CONF bit 2).
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esp.MODEM_LPCON.SetCLK_CONF_CLK_I2C_MST_EN(1)
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// Enable the master's own clock gate (LP_I2C_ANA_MST.DATE bit 28).
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esp.LP_I2C_ANA_MST.SetDATE_LP_I2C_ANA_MAST_I2C_MAT_CLK_EN(1)
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// Enable the SAR ADC slave device (DEVICE_EN bit 7).
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dev := esp.LP_I2C_ANA_MST.GetDEVICE_EN_LP_I2C_ANA_MAST_I2C_DEVICE_EN()
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esp.LP_I2C_ANA_MST.SetDEVICE_EN_LP_I2C_ANA_MAST_I2C_DEVICE_EN(dev | c6SarI2CDeviceEn)
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}
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// writeMask implements the REGI2C_WRITE_MASK macro for ESP32-C6 via LP_I2C_ANA_MST.
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// It reads the current byte at regAddr, updates the [msb:lsb] bitfield, and writes
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// it back. Matches esp_rom_regi2c_write_mask() in esp_rom_regi2c_esp32c6.c.
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func (r regI2C) writeMask(regAddr, msb, lsb, data uint8) {
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ctrl := &esp.LP_I2C_ANA_MST.I2C0_CTRL
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rdata := &esp.LP_I2C_ANA_MST.I2C0_DATA
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// Issue a read command: slave_id | (reg_addr << 8), no WR_CNTL bit.
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readCmd := (uint32(i2cSarADC) << c6SlaveIDShift) | (uint32(regAddr) << c6AddrShift)
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volatile.StoreUint32(&ctrl.Reg, readCmd)
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for volatile.LoadUint32(&ctrl.Reg)&c6BusyBit != 0 {
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}
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cur := volatile.LoadUint32(&rdata.Reg) & 0xFF
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// Modify the [msb:lsb] bitfield.
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mask := uint32(1<<(msb-lsb+1)-1) << lsb
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cur &^= mask
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cur |= uint32(data&(1<<(msb-lsb+1)-1)) << lsb
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// Issue a write command: slave_id | (reg_addr<<8) | WR_CNTL | (data<<16).
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writeCmd := (uint32(i2cSarADC) << c6SlaveIDShift) |
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(uint32(regAddr) << c6AddrShift) |
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(uint32(1) << c6WrCntlShift) |
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((cur & 0xFF) << c6DataShift)
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volatile.StoreUint32(&ctrl.Reg, writeCmd)
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for volatile.LoadUint32(&ctrl.Reg)&c6BusyBit != 0 {
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}
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}
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// calibrationInit sets the DREF reference for the selected ADC unit.
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func (r regI2C) calibrationInit(adcN uint8) {
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if adcN == 0 {
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r.writeMask(adc1DrefAddr, adc1DrefMSB, adc1DrefLSB, r.drefInit)
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} else {
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r.writeMask(adc2DrefAddr, adc2DrefMSB, adc2DrefLSB, r.drefInit)
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}
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}
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// calibrationPrepare enables ENCAL_GND so the ADC input is shorted to ground.
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func (r regI2C) calibrationPrepare(adcN uint8) {
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if adcN == 0 {
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r.writeMask(adc1EncalGndAddr, adc1EncalGndMSB, adc1EncalGndLSB, 1)
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} else {
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r.writeMask(adc2EncalGndAddr, adc2EncalGndMSB, adc2EncalGndLSB, 1)
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}
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}
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// calibrationFinish clears ENCAL_GND to reconnect the ADC input to the pad.
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func (r regI2C) calibrationFinish(adcN uint8) {
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if adcN == 0 {
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r.writeMask(adc1EncalGndAddr, adc1EncalGndMSB, adc1EncalGndLSB, 0)
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} else {
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r.writeMask(adc2EncalGndAddr, adc2EncalGndMSB, adc2EncalGndLSB, 0)
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}
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}
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// setCalibrationParam writes the INIT_CODE (offset trim) for the selected ADC unit.
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func (r regI2C) setCalibrationParam(adcN uint8, param uint32) {
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msb := uint8(param >> 8)
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lsb := uint8(param & 0xFF)
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if adcN == 0 {
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r.writeMask(adc1InitCodeHighAddr, adc1InitCodeHighMSB, adc1InitCodeHighLSB, msb)
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r.writeMask(adc1InitCodeLowAddr, adc1InitCodeLowMSB, adc1InitCodeLowLSB, lsb)
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} else {
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r.writeMask(adc2InitCodeHighAddr, adc2InitCodeHighMSB, adc2InitCodeHighLSB, msb)
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r.writeMask(adc2InitCodeLowAddr, adc2InitCodeLowMSB, adc2InitCodeLowLSB, lsb)
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}
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}
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// calibrateBinarySearch runs the ADC self-calibration binary search loop.
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// It performs 'iterations' rounds, drops the min/max outliers, and returns
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// the rounded mean of the remaining values. Matches adc_hal_self_calibration().
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func (r regI2C) calibrateBinarySearch(adcN uint8, iterations int, readADC func() uint32) uint32 {
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if iterations > adcCalMaxIterations {
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iterations = adcCalMaxIterations
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}
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var codeList [adcCalMaxIterations]uint32
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var codeSum uint32
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for rpt := 0; rpt < iterations; rpt++ {
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codeH := adcCalOffsetRange
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codeL := uint32(0)
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chkCode := (codeH + codeL) / 2
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r.setCalibrationParam(adcN, chkCode)
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selfCal := readADC()
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for codeH-codeL > 1 {
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if selfCal == 0 {
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codeH = chkCode
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} else {
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codeL = chkCode
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}
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chkCode = (codeH + codeL) / 2
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r.setCalibrationParam(adcN, chkCode)
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selfCal = readADC()
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if codeH-codeL == 1 {
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chkCode++
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r.setCalibrationParam(adcN, chkCode)
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selfCal = readADC()
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}
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}
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codeList[rpt] = chkCode
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codeSum += chkCode
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}
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codeMin := codeList[0]
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codeMax := codeList[0]
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for i := 0; i < iterations; i++ {
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if codeList[i] < codeMin {
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codeMin = codeList[i]
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}
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if codeList[i] > codeMax {
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codeMax = codeList[i]
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}
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}
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remaining := codeSum - codeMax - codeMin
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divisor := uint32(iterations - 2)
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finalCode := remaining / divisor
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if remaining%divisor >= 4 {
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finalCode++
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}
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return finalCode
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}
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// ── Self-calibration ──────────────────────────────────────────────────────────
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const (
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adcCalTimesC6 = 15
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adcCalRtcMagicC6 = uint32(0xADC1C601) // magic distinguishes C6 from C3
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adcCalInitMinC6 = uint32(1000)
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adcCalInitMaxC6 = uint32(4096)
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)
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// adcSelfCalibrate runs a self-calibration for ADC1 (the only ADC unit on C6).
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// The calibration code is cached in LP_AON scratch registers to survive sleep.
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// eFuse calibration is not used: the fields are often unprogrammed.
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func adcSelfCalibrate() {
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reg := newRegI2C()
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reg.sarEnable()
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var adc1Code uint32
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if saved, ok := c6RestoreFromLP(); ok {
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adc1Code = saved
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} else {
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c6CalSetupADC1()
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reg.calibrationInit(0)
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reg.calibrationPrepare(0)
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adc1Code = reg.calibrateBinarySearch(0, adcCalTimesC6, readADC1)
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if adc1Code < adcCalInitMinC6 {
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adc1Code = adcCalInitMinC6
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}
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if adc1Code > adcCalInitMaxC6 {
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adc1Code = adcCalInitMaxC6
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}
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c6SaveToLP(adc1Code)
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reg.calibrationFinish(0)
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}
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c6ApplyADC1Code(reg, adc1Code)
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}
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// c6CalSetupADC1 configures APB_SARADC for oneshot ADC1 ch0 with fixed attenuation.
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func c6CalSetupADC1() {
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esp.APB_SARADC.SetONETIME_SAMPLE_SARADC_ONETIME_ATTEN(atten11dB)
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esp.APB_SARADC.SetONETIME_SAMPLE_SARADC_ONETIME_CHANNEL(0)
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esp.APB_SARADC.SetONETIME_SAMPLE_SARADC1_ONETIME_SAMPLE(1)
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}
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// readADC1 performs a single ADC1 conversion and returns the raw 12-bit result.
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func readADC1() uint32 {
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esp.APB_SARADC.SetINT_CLR_APB_SARADC1_DONE_INT_CLR(1)
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esp.APB_SARADC.SetONETIME_SAMPLE_SARADC_ONETIME_START(0)
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esp.APB_SARADC.SetONETIME_SAMPLE_SARADC_ONETIME_START(1)
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for esp.APB_SARADC.GetINT_RAW_APB_SARADC1_DONE_INT_RAW() == 0 {
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}
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raw := esp.APB_SARADC.GetSAR1DATA_STATUS_APB_SARADC1_DATA() & 0xfff
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esp.APB_SARADC.SetONETIME_SAMPLE_SARADC_ONETIME_START(0)
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return uint32(raw)
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}
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// c6RestoreFromLP reads the saved calibration code from LP_AON scratch registers.
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// On C6, LP_AON replaces the C3's RTC_CNTL for scratch storage.
|
||||
func c6RestoreFromLP() (uint32, bool) {
|
||||
if esp.LP_AON.GetSTORE0() != adcCalRtcMagicC6 {
|
||||
return 0, false
|
||||
}
|
||||
code := esp.LP_AON.GetSTORE1()
|
||||
if code < adcCalInitMinC6 || code > adcCalInitMaxC6 {
|
||||
return 0, false
|
||||
}
|
||||
return code, true
|
||||
}
|
||||
|
||||
// c6SaveToLP stores the calibration code in LP_AON scratch registers.
|
||||
func c6SaveToLP(code uint32) {
|
||||
if code < adcCalInitMinC6 || code > adcCalInitMaxC6 {
|
||||
return
|
||||
}
|
||||
esp.LP_AON.SetSTORE0(adcCalRtcMagicC6)
|
||||
esp.LP_AON.SetSTORE1(code)
|
||||
}
|
||||
|
||||
// c6ApplyADC1Code sets ADC1 init code and finishes calibration.
|
||||
// ESP32-C6 has no ADC2 so only ADC1 (adcN=0) needs to be configured.
|
||||
func c6ApplyADC1Code(reg regI2C, code uint32) {
|
||||
c6CalSetupADC1()
|
||||
reg.calibrationInit(0)
|
||||
reg.calibrationPrepare(0)
|
||||
reg.setCalibrationParam(0, code)
|
||||
reg.calibrationFinish(0)
|
||||
}
|
||||
Reference in New Issue
Block a user