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https://github.com/tinygo-org/drivers.git
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soypat
100 lines
4.6 KiB
Go
100 lines
4.6 KiB
Go
package l3gd20
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// Expected identification number for L3GD20.
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const (
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// For L3GD20
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expectedWHOAMI = 0xD4
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// For L3GD20H
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expectedWHOAMI_H = 0xD7
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)
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// Register bits masks
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const (
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reg5RebootBit = 1 << 7
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reg5FIFOEnableBit = 1 << 6
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reg1NormalBits = 0b1111
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)
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// Register addresses. Comments from https://github.com/adafruit/Adafruit_L3GD20_U/blob/master/Adafruit_L3GD20_U.cpp
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const (
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// The Slave ADdress (SAD) associated with the L3GD20 is 110101xb
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I2CAddr = 0b1101011
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// The SDO pin can be used to modify the less significant bit of the device address.
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I2CAddrSDOLow = 0b1101010
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WHOAMI uint8 = 0x0F
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// CTRL_REG1 (0x20)
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// ====================================================================
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// BIT Symbol Description Default
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// --- ------ --------------------------------------------- -------
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// 7-6 DR1/0 Output data rate 00
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// 5-4 BW1/0 Bandwidth selection 00
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// 3 PD 0 = Power-down mode, 1 = normal/sleep mode 0
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// 2 ZEN Z-axis enable (0 = disabled, 1 = enabled) 1
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// 1 YEN Y-axis enable (0 = disabled, 1 = enabled) 1
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// 0 XEN X-axis enable (0 = disabled, 1 = enabled) 1
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CTRL_REG1 uint8 = 0x20
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// Set CTRL_REG2 (0x21)
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// ====================================================================
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// BIT Symbol Description Default
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// --- ------ --------------------------------------------- -------
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// 5-4 HPM1/0 High-pass filter mode selection 00
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// 3-0 HPCF3..0 High-pass filter cutoff frequency selection 0000
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CTRL_REG2 uint8 = 0x21
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// CTRL_REG3 (0x22)
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// ====================================================================
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// BIT Symbol Description Default
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// --- ------ --------------------------------------------- -------
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// 7 I1_Int1 Interrupt enable on INT1 (0=disable,1=enable) 0
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// 6 I1_Boot Boot status on INT1 (0=disable,1=enable) 0
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// 5 H-Lactive Interrupt active config on INT1 (0=high,1=low) 0
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// 4 PP_OD Push-Pull/Open-Drain (0=PP, 1=OD) 0
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// 3 I2_DRDY Data ready on DRDY/INT2 (0=disable,1=enable) 0
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// 2 I2_WTM FIFO wtrmrk int on DRDY/INT2 (0=dsbl,1=enbl) 0
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// 1 I2_ORun FIFO overrun int on DRDY/INT2 (0=dsbl,1=enbl) 0
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// 0 I2_Empty FIFI empty int on DRDY/INT2 (0=dsbl,1=enbl) 0
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CTRL_REG3 uint8 = 0x22
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// CTRL_REG4 (0x23)
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// ====================================================================
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// BIT Symbol Description Default
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// --- ------ --------------------------------------------- -------
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// 7 BDU Block Data Update (0=continuous, 1=LSB/MSB) 0
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// 6 BLE Big/Little-Endian (0=Data LSB, 1=Data MSB) 0
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// 5-4 FS1/0 Full scale selection 00
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// 00 = 250 dps
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// 01 = 500 dps
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// 10 = 2000 dps
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// 11 = 2000 dps
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// 0 SIM SPI Mode (0=4-wire, 1=3-wire) 0
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CTRL_REG4 uint8 = 0x23
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// CTRL_REG5 (0x24)
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// ====================================================================
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// BIT Symbol Description Default
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// --- ------ --------------------------------------------- -------
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// 7 BOOT Reboot memory content (0=normal, 1=reboot) 0
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// 6 FIFO_EN FIFO enable (0=FIFO disable, 1=enable) 0
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// 4 HPen High-pass filter enable (0=disable,1=enable) 0
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// 3-2 INT1_SEL INT1 Selection config 00
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// 1-0 OUT_SEL Out selection config 00
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CTRL_REG5 uint8 = 0x24
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REFERENCE uint8 = 0x25
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OUT_TEMP uint8 = 0x26
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STATUS_REG uint8 = 0x27
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OUT_X_L uint8 = 0x28
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OUT_X_H uint8 = 0x29
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OUT_Y_L uint8 = 0x2A
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OUT_Y_H uint8 = 0x2B
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OUT_Z_L uint8 = 0x2C
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OUT_Z_H uint8 = 0x2D
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FIFO_CTRL_REG uint8 = 0x2E
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FIFO_SRC_REG uint8 = 0x2F
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INT1_CFG uint8 = 0x30
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INT1_SRC uint8 = 0x31
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INT1_TSH_XH uint8 = 0x32
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INT1_TSH_XL uint8 = 0x33
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INT1_TSH_YH uint8 = 0x34
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INT1_TSH_YL uint8 = 0x35
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INT1_TSH_ZH uint8 = 0x36
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INT1_TSH_ZL uint8 = 0x37
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INT1_DURATION uint8 = 0x38
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)
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