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deadprogram
123 lines
2.1 KiB
Go
123 lines
2.1 KiB
Go
package si5351
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// The I2C address which this device listens to.
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const AddressDefault = 0x60 // Assumes ADDR pin is low
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const AddressAlternative = 0x61 // Assumes ADDR pin is high
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const (
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OUTPUT_ENABLE_CONTROL = 3
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CLK0_CONTROL = 16
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CLK1_CONTROL = 17
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CLK2_CONTROL = 18
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CLK3_CONTROL = 19
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CLK4_CONTROL = 20
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CLK5_CONTROL = 21
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CLK6_CONTROL = 22
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CLK7_CONTROL = 23
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MULTISYNTH0_PARAMETERS_1 = 42
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MULTISYNTH0_PARAMETERS_3 = 44
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MULTISYNTH1_PARAMETERS_1 = 50
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MULTISYNTH1_PARAMETERS_3 = 52
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MULTISYNTH2_PARAMETERS_1 = 58
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MULTISYNTH2_PARAMETERS_3 = 60
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SPREAD_SPECTRUM_PARAMETERS = 149
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PLL_RESET = 177
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CRYSTAL_INTERNAL_LOAD_CAPACITANCE = 183
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FANOUT_ENABLE = 187
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)
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const (
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CRYSTAL_LOAD_6PF = (1 << 6)
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CRYSTAL_LOAD_8PF = (2 << 6)
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CRYSTAL_LOAD_10PF = (3 << 6)
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)
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const (
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CRYSTAL_FREQ_25MHZ = 25000000
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CRYSTAL_FREQ_27MHZ = 27000000
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)
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const (
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PLL_A = iota
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PLL_B
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)
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const (
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R_DIV_1 = iota
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R_DIV_2
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R_DIV_4
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R_DIV_8
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R_DIV_16
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R_DIV_32
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R_DIV_64
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R_DIV_128
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)
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const (
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MULTISYNTH_DIV_4 = 4
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MULTISYNTH_DIV_6 = 6
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MULTISYNTH_DIV_8 = 8
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)
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// Frequency constants (in Hz)
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const (
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CLKOUT_MIN_FREQ = 8000 // 8 kHz
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CLKOUT_MAX_FREQ = 150000000 // 150 MHz
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MULTISYNTH_MAX_FREQ = 150000000 // 150 MHz
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MULTISYNTH_SHARE_MAX = 100000000 // 100 MHz
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MULTISYNTH_DIVBY4_FREQ = 150000000 // 150 MHz
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PLL_VCO_MIN = 600000000 // 600 MHz
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PLL_VCO_MAX = 900000000 // 900 MHz
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)
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const (
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SI5351_PLL_C_MAX = 1048575
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)
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// Bit masks for FANOUT_ENABLE register
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const (
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CLKIN_ENABLE = (1 << 7)
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XTAL_ENABLE = (1 << 6)
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MULTISYNTH_ENABLE = (1 << 4)
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)
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const (
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FANOUT_CLKIN = iota
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FANOUT_XO
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FANOUT_MS
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)
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// Clock source selection masks for CLKx_CONTROL registers
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const (
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CLK_INPUT_MASK = 0x3 // Bits 0 and 1
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CLK_INPUT_XTAL = 0x0
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CLK_INPUT_CLKIN = 0x1
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CLK_INPUT_MULTISYNTH_0_4 = 0x2
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CLK_INPUT_MULTISYNTH_N = 0x3
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)
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// Clock source selection
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const (
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CLK_SRC_XTAL = iota
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CLK_SRC_CLKIN
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CLK_SRC_MS0
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CLK_SRC_MS
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)
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const (
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CLK_INVERT = 1 << 4
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)
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const (
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CLK_DRIVE_STRENGTH_2MA = 0
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CLK_DRIVE_STRENGTH_4MA = 1
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CLK_DRIVE_STRENGTH_6MA = 2
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CLK_DRIVE_STRENGTH_8MA = 3
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)
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