package si5351 // The I2C address which this device listens to. const AddressDefault = 0x60 // Assumes ADDR pin is low const AddressAlternative = 0x61 // Assumes ADDR pin is high const ( XTAL_FREQ = 25000000 PLL_FIXED = 80000000000 FREQ_MULT = 100 DEFAULT_CLK = 1000000000 PLL_VCO_MIN = 600000000 PLL_VCO_MAX = 900000000 MULTISYNTH_MIN_FREQ = 500000 MULTISYNTH_DIVBY4_FREQ = 150000000 MULTISYNTH_MAX_FREQ = 225000000 MULTISYNTH_SHARE_MAX = 100000000 MULTISYNTH_SHARE_MIN = 1024000 MULTISYNTH67_MAX_FREQ = MULTISYNTH_DIVBY4_FREQ CLKOUT_MIN_FREQ = 4000 CLKOUT_MAX_FREQ = MULTISYNTH_MAX_FREQ CLKOUT67_MS_MIN = PLL_VCO_MIN / MULTISYNTH67_A_MAX CLKOUT67_MIN_FREQ = CLKOUT67_MS_MIN / 128 CLKOUT67_MAX_FREQ = MULTISYNTH67_MAX_FREQ PLL_A_MIN = 15 PLL_A_MAX = 90 PLL_B_MAX = PLL_C_MAX - 1 PLL_C_MAX = 1048575 MULTISYNTH_A_MIN = 6 MULTISYNTH_A_MAX = 1800 MULTISYNTH67_A_MAX = 254 MULTISYNTH_B_MAX = MULTISYNTH_C_MAX - 1 MULTISYNTH_C_MAX = 1048575 MULTISYNTH_P1_MAX = (1 << 18) - 1 MULTISYNTH_P2_MAX = (1 << 20) - 1 MULTISYNTH_P3_MAX = (1 << 20) - 1 VCXO_PULL_MIN = 30 VCXO_PULL_MAX = 240 VCXO_MARGIN = 103 DEVICE_STATUS = 0 INTERRUPT_STATUS = 1 INTERRUPT_MASK = 2 STATUS_SYS_INIT = 1 << 7 STATUS_LOL_B = 1 << 6 STATUS_LOL_A = 1 << 5 STATUS_LOS = 1 << 4 OUTPUT_ENABLE_CTRL = 3 OEB_PIN_ENABLE_CTRL = 9 PLL_INPUT_SOURCE = 15 CLKIN_DIV_MASK = 3 << 6 CLKIN_DIV_1 = 0 << 6 CLKIN_DIV_2 = 1 << 6 CLKIN_DIV_4 = 2 << 6 CLKIN_DIV_8 = 3 << 6 PLLB_SOURCE = 1 << 3 PLLA_SOURCE = 1 << 2 CLK0_CTRL = 16 CLK1_CTRL = 17 CLK2_CTRL = 18 CLK3_CTRL = 19 CLK4_CTRL = 20 CLK5_CTRL = 21 CLK6_CTRL = 22 CLK7_CTRL = 23 CLK_POWERDOWN = 1 << 7 CLK_INTEGER_MODE = 1 << 6 CLK_PLL_SELECT = 1 << 5 CLK_INVERT = 1 << 4 CLK_INPUT_MASK = 3 << 2 CLK_INPUT_XTAL = 0 << 2 CLK_INPUT_CLKIN = 1 << 2 CLK_INPUT_MULTISYNTH_0_4 = 2 << 2 CLK_INPUT_MULTISYNTH_N = 3 << 2 CLK_DRIVE_STRENGTH_MASK = 3 << 0 CLK_DRIVE_STRENGTH_2MA = 0 << 0 CLK_DRIVE_STRENGTH_4MA = 1 << 0 CLK_DRIVE_STRENGTH_6MA = 2 << 0 CLK_DRIVE_STRENGTH_8MA = 3 << 0 CLK3_0_DISABLE_STATE = 24 CLK7_4_DISABLE_STATE = 25 CLK_DISABLE_STATE_MASK = 3 CLK_DISABLE_STATE_LOW = 0 CLK_DISABLE_STATE_HIGH = 1 CLK_DISABLE_STATE_FLOAT = 2 CLK_DISABLE_STATE_NEVER = 3 PARAMETERS_LENGTH = 8 PLLA_PARAMETERS = 26 PLLB_PARAMETERS = 34 CLK0_PARAMETERS = 42 CLK1_PARAMETERS = 50 CLK2_PARAMETERS = 58 CLK3_PARAMETERS = 66 CLK4_PARAMETERS = 74 CLK5_PARAMETERS = 82 CLK6_PARAMETERS = 90 CLK7_PARAMETERS = 91 CLK6_7_OUTPUT_DIVIDER = 92 OUTPUT_CLK_DIV_MASK = 7 << 4 OUTPUT_CLK6_DIV_MASK = 7 << 0 OUTPUT_CLK_DIV_SHIFT = 4 OUTPUT_CLK_DIV6_SHIFT = 0 OUTPUT_CLK_DIV_1 = 0 OUTPUT_CLK_DIV_2 = 1 OUTPUT_CLK_DIV_4 = 2 OUTPUT_CLK_DIV_8 = 3 OUTPUT_CLK_DIV_16 = 4 OUTPUT_CLK_DIV_32 = 5 OUTPUT_CLK_DIV_64 = 6 OUTPUT_CLK_DIV_128 = 7 OUTPUT_CLK_DIVBY4 = 3 << 2 SSC_PARAM0 = 149 SSC_PARAM1 = 150 SSC_PARAM2 = 151 SSC_PARAM3 = 152 SSC_PARAM4 = 153 SSC_PARAM5 = 154 SSC_PARAM6 = 155 SSC_PARAM7 = 156 SSC_PARAM8 = 157 SSC_PARAM9 = 158 SSC_PARAM10 = 159 SSC_PARAM11 = 160 SSC_PARAM12 = 161 VXCO_PARAMETERS_LOW = 162 VXCO_PARAMETERS_MID = 163 VXCO_PARAMETERS_HIGH = 164 CLK0_PHASE_OFFSET = 165 CLK1_PHASE_OFFSET = 166 CLK2_PHASE_OFFSET = 167 CLK3_PHASE_OFFSET = 168 CLK4_PHASE_OFFSET = 169 CLK5_PHASE_OFFSET = 170 PLL_RESET = 177 PLL_RESET_B = 1 << 7 PLL_RESET_A = 1 << 5 CRYSTAL_LOAD = 183 CRYSTAL_LOAD_MASK = 3 << 6 CRYSTAL_LOAD_0PF = 0 << 6 CRYSTAL_LOAD_6PF = 1 << 6 CRYSTAL_LOAD_8PF = 2 << 6 CRYSTAL_LOAD_10PF = 3 << 6 FANOUT_ENABLE = 187 CLKIN_ENABLE = 1 << 7 XTAL_ENABLE = 1 << 6 MULTISYNTH_ENABLE = 1 << 4 )