mirror of
https://github.com/tinygo-org/drivers.git
synced 2026-08-14 03:43:42 +00:00
si5351: complete refactor for more complete interface
This completely refactors the interface and implementation for the si5351 clock generator. The interface based on the Arduino implementation was both somewhat hard to work with and also missing a number of important features that are needed to use this chip for RF communication. Instead this new implementation draws inspiration from the efforts of the Traquino community mostly using the rp2040 processor. The TinyGo implementation is based on the patterns and code in the drivers repo for other i2c devices. It also includes some basic unit tests which are not comprehensive but at least provide some coverage. Signed-off-by: deadprogram <ron@hybridgroup.com>
This commit is contained in:
deadprogram
+145
-66
@@ -5,75 +5,154 @@ const AddressDefault = 0x60 // Assumes ADDR pin is low
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const AddressAlternative = 0x61 // Assumes ADDR pin is high
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const (
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OUTPUT_ENABLE_CONTROL = 3
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XTAL_FREQ = 25000000
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PLL_FIXED = 80000000000
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FREQ_MULT = 100
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DEFAULT_CLK = 1000000000
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CLK0_CONTROL = 16
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CLK1_CONTROL = 17
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CLK2_CONTROL = 18
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CLK3_CONTROL = 19
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CLK4_CONTROL = 20
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CLK5_CONTROL = 21
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CLK6_CONTROL = 22
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CLK7_CONTROL = 23
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PLL_VCO_MIN = 600000000
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PLL_VCO_MAX = 900000000
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MULTISYNTH_MIN_FREQ = 500000
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MULTISYNTH_DIVBY4_FREQ = 150000000
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MULTISYNTH_MAX_FREQ = 225000000
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MULTISYNTH_SHARE_MAX = 100000000
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MULTISYNTH_SHARE_MIN = 1024000
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MULTISYNTH67_MAX_FREQ = MULTISYNTH_DIVBY4_FREQ
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CLKOUT_MIN_FREQ = 4000
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CLKOUT_MAX_FREQ = MULTISYNTH_MAX_FREQ
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CLKOUT67_MS_MIN = PLL_VCO_MIN / MULTISYNTH67_A_MAX
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CLKOUT67_MIN_FREQ = CLKOUT67_MS_MIN / 128
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CLKOUT67_MAX_FREQ = MULTISYNTH67_MAX_FREQ
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MULTISYNTH0_PARAMETERS_1 = 42
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MULTISYNTH0_PARAMETERS_3 = 44
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MULTISYNTH1_PARAMETERS_1 = 50
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MULTISYNTH1_PARAMETERS_3 = 52
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MULTISYNTH2_PARAMETERS_1 = 58
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MULTISYNTH2_PARAMETERS_3 = 60
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PLL_A_MIN = 15
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PLL_A_MAX = 90
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PLL_B_MAX = PLL_C_MAX - 1
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PLL_C_MAX = 1048575
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MULTISYNTH_A_MIN = 6
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MULTISYNTH_A_MAX = 1800
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MULTISYNTH67_A_MAX = 254
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MULTISYNTH_B_MAX = MULTISYNTH_C_MAX - 1
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MULTISYNTH_C_MAX = 1048575
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MULTISYNTH_P1_MAX = (1 << 18) - 1
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MULTISYNTH_P2_MAX = (1 << 20) - 1
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MULTISYNTH_P3_MAX = (1 << 20) - 1
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VCXO_PULL_MIN = 30
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VCXO_PULL_MAX = 240
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VCXO_MARGIN = 103
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SPREAD_SPECTRUM_PARAMETERS = 149
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DEVICE_STATUS = 0
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INTERRUPT_STATUS = 1
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INTERRUPT_MASK = 2
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STATUS_SYS_INIT = 1 << 7
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STATUS_LOL_B = 1 << 6
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STATUS_LOL_A = 1 << 5
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STATUS_LOS = 1 << 4
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OUTPUT_ENABLE_CTRL = 3
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OEB_PIN_ENABLE_CTRL = 9
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PLL_INPUT_SOURCE = 15
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CLKIN_DIV_MASK = 3 << 6
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CLKIN_DIV_1 = 0 << 6
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CLKIN_DIV_2 = 1 << 6
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CLKIN_DIV_4 = 2 << 6
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CLKIN_DIV_8 = 3 << 6
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PLLB_SOURCE = 1 << 3
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PLLA_SOURCE = 1 << 2
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PLL_RESET = 177
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CLK0_CTRL = 16
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CLK1_CTRL = 17
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CLK2_CTRL = 18
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CLK3_CTRL = 19
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CLK4_CTRL = 20
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CLK5_CTRL = 21
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CLK6_CTRL = 22
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CLK7_CTRL = 23
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CLK_POWERDOWN = 1 << 7
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CLK_INTEGER_MODE = 1 << 6
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CLK_PLL_SELECT = 1 << 5
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CLK_INVERT = 1 << 4
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CLK_INPUT_MASK = 3 << 2
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CLK_INPUT_XTAL = 0 << 2
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CLK_INPUT_CLKIN = 1 << 2
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CLK_INPUT_MULTISYNTH_0_4 = 2 << 2
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CLK_INPUT_MULTISYNTH_N = 3 << 2
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CLK_DRIVE_STRENGTH_MASK = 3 << 0
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CLK_DRIVE_STRENGTH_2MA = 0 << 0
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CLK_DRIVE_STRENGTH_4MA = 1 << 0
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CLK_DRIVE_STRENGTH_6MA = 2 << 0
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CLK_DRIVE_STRENGTH_8MA = 3 << 0
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CRYSTAL_INTERNAL_LOAD_CAPACITANCE = 183
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)
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const (
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CRYSTAL_LOAD_6PF = (1 << 6)
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CRYSTAL_LOAD_8PF = (2 << 6)
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CRYSTAL_LOAD_10PF = (3 << 6)
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)
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const (
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CRYSTAL_FREQ_25MHZ = 25000000
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CRYSTAL_FREQ_27MHZ = 27000000
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)
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const (
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PLL_A = iota
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PLL_B
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)
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const (
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R_DIV_1 = iota
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R_DIV_2
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R_DIV_4
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R_DIV_8
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R_DIV_16
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R_DIV_32
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R_DIV_64
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R_DIV_128
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)
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const (
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MULTISYNTH_DIV_4 = 4
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MULTISYNTH_DIV_6 = 6
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MULTISYNTH_DIV_8 = 8
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)
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// Frequency constants (in Hz)
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const (
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CLKOUT_MIN_FREQ = 8000 // 8 kHz
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CLKOUT_MAX_FREQ = 150000000 // 150 MHz
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MULTISYNTH_MAX_FREQ = 150000000 // 150 MHz
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MULTISYNTH_SHARE_MAX = 100000000 // 100 MHz
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MULTISYNTH_DIVBY4_FREQ = 150000000 // 150 MHz
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PLL_VCO_MIN = 600000000 // 600 MHz
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PLL_VCO_MAX = 900000000 // 900 MHz
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)
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const (
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SI5351_PLL_C_MAX = 1048575
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CLK3_0_DISABLE_STATE = 24
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CLK7_4_DISABLE_STATE = 25
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CLK_DISABLE_STATE_MASK = 3
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CLK_DISABLE_STATE_LOW = 0
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CLK_DISABLE_STATE_HIGH = 1
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CLK_DISABLE_STATE_FLOAT = 2
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CLK_DISABLE_STATE_NEVER = 3
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PARAMETERS_LENGTH = 8
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PLLA_PARAMETERS = 26
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PLLB_PARAMETERS = 34
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CLK0_PARAMETERS = 42
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CLK1_PARAMETERS = 50
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CLK2_PARAMETERS = 58
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CLK3_PARAMETERS = 66
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CLK4_PARAMETERS = 74
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CLK5_PARAMETERS = 82
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CLK6_PARAMETERS = 90
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CLK7_PARAMETERS = 91
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CLK6_7_OUTPUT_DIVIDER = 92
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OUTPUT_CLK_DIV_MASK = 7 << 4
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OUTPUT_CLK6_DIV_MASK = 7 << 0
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OUTPUT_CLK_DIV_SHIFT = 4
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OUTPUT_CLK_DIV6_SHIFT = 0
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OUTPUT_CLK_DIV_1 = 0
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OUTPUT_CLK_DIV_2 = 1
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OUTPUT_CLK_DIV_4 = 2
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OUTPUT_CLK_DIV_8 = 3
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OUTPUT_CLK_DIV_16 = 4
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OUTPUT_CLK_DIV_32 = 5
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OUTPUT_CLK_DIV_64 = 6
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OUTPUT_CLK_DIV_128 = 7
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OUTPUT_CLK_DIVBY4 = 3 << 2
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SSC_PARAM0 = 149
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SSC_PARAM1 = 150
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SSC_PARAM2 = 151
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SSC_PARAM3 = 152
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SSC_PARAM4 = 153
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SSC_PARAM5 = 154
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SSC_PARAM6 = 155
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SSC_PARAM7 = 156
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SSC_PARAM8 = 157
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SSC_PARAM9 = 158
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SSC_PARAM10 = 159
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SSC_PARAM11 = 160
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SSC_PARAM12 = 161
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VXCO_PARAMETERS_LOW = 162
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VXCO_PARAMETERS_MID = 163
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VXCO_PARAMETERS_HIGH = 164
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CLK0_PHASE_OFFSET = 165
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CLK1_PHASE_OFFSET = 166
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CLK2_PHASE_OFFSET = 167
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CLK3_PHASE_OFFSET = 168
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CLK4_PHASE_OFFSET = 169
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CLK5_PHASE_OFFSET = 170
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PLL_RESET = 177
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PLL_RESET_B = 1 << 7
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PLL_RESET_A = 1 << 5
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CRYSTAL_LOAD = 183
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CRYSTAL_LOAD_MASK = 3 << 6
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CRYSTAL_LOAD_0PF = 0 << 6
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CRYSTAL_LOAD_6PF = 1 << 6
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CRYSTAL_LOAD_8PF = 2 << 6
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CRYSTAL_LOAD_10PF = 3 << 6
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FANOUT_ENABLE = 187
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CLKIN_ENABLE = 1 << 7
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XTAL_ENABLE = 1 << 6
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MULTISYNTH_ENABLE = 1 << 4
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)
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+996
-556
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,214 @@
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package si5351
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import (
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"testing"
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)
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func TestSelectRDiv(t *testing.T) {
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d := &Device{}
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tests := []struct {
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name string
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freq Frequency
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wantDiv uint8
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wantFreq Frequency
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}{
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{"4kHz", 4000 * FREQ_MULT, OUTPUT_CLK_DIV_128, 4000 * FREQ_MULT * 128},
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{"8kHz", 8000 * FREQ_MULT, OUTPUT_CLK_DIV_64, 8000 * FREQ_MULT * 64},
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{"16kHz", 16000 * FREQ_MULT, OUTPUT_CLK_DIV_32, 16000 * FREQ_MULT * 32},
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{"32kHz", 32000 * FREQ_MULT, OUTPUT_CLK_DIV_16, 32000 * FREQ_MULT * 16},
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{"64kHz", 64000 * FREQ_MULT, OUTPUT_CLK_DIV_8, 64000 * FREQ_MULT * 8},
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{"128kHz", 128000 * FREQ_MULT, OUTPUT_CLK_DIV_4, 128000 * FREQ_MULT * 4},
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{"256kHz", 256000 * FREQ_MULT, OUTPUT_CLK_DIV_2, 256000 * FREQ_MULT * 2},
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{"512kHz", 512000 * FREQ_MULT, OUTPUT_CLK_DIV_1, 512000 * FREQ_MULT},
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{"1MHz", 1000000 * FREQ_MULT, OUTPUT_CLK_DIV_1, 1000000 * FREQ_MULT},
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}
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for _, tt := range tests {
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t.Run(tt.name, func(t *testing.T) {
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freq := tt.freq
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freq, gotDiv := d.selectRDiv(freq)
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if gotDiv != tt.wantDiv {
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t.Errorf("selectRDiv() div = %v, want %v", gotDiv, tt.wantDiv)
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}
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if freq != tt.wantFreq {
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t.Errorf("selectRDiv() freq = %v, want %v", freq, tt.wantFreq)
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}
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})
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}
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}
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func TestSelectRDivMS67(t *testing.T) {
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d := &Device{}
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tests := []struct {
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name string
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freq Frequency
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wantDiv uint8
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wantFreq Frequency
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}{
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{"4kHz", 4000 * FREQ_MULT, OUTPUT_CLK_DIV_128, 4000 * FREQ_MULT * 128},
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{"8kHz", 8000 * FREQ_MULT, OUTPUT_CLK_DIV_64, 8000 * FREQ_MULT * 64},
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{"16kHz", 16000 * FREQ_MULT, OUTPUT_CLK_DIV_32, 16000 * FREQ_MULT * 32},
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{"64kHz", 64000 * FREQ_MULT, OUTPUT_CLK_DIV_8, 64000 * FREQ_MULT * 8},
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{"256kHz", 256000 * FREQ_MULT, OUTPUT_CLK_DIV_2, 256000 * FREQ_MULT * 2},
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{"512kHz", 512000 * FREQ_MULT, OUTPUT_CLK_DIV_1, 512000 * FREQ_MULT},
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{"1MHz", 1000000 * FREQ_MULT, OUTPUT_CLK_DIV_1, 1000000 * FREQ_MULT},
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}
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for _, tt := range tests {
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t.Run(tt.name, func(t *testing.T) {
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freq := tt.freq
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freq, gotDiv := d.selectRDivMS67(freq)
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if gotDiv != tt.wantDiv {
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t.Errorf("selectRDivMS67() div = %v, want %v", gotDiv, tt.wantDiv)
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}
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if freq != tt.wantFreq {
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t.Errorf("selectRDivMS67() freq = %v, want %v", freq, tt.wantFreq)
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}
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})
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}
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}
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func TestCalculatePLL(t *testing.T) {
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d := &Device{}
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d.crystalFreq[0] = 25000000
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tests := []struct {
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name string
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freq Frequency
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wantMin Frequency
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wantMax Frequency
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}{
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{"600MHz", 600000000 * FREQ_MULT, 599000000 * FREQ_MULT, 601000000 * FREQ_MULT},
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{"750MHz", 750000000 * FREQ_MULT, 749000000 * FREQ_MULT, 751000000 * FREQ_MULT},
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{"900MHz", 900000000 * FREQ_MULT, 899000000 * FREQ_MULT, 901000000 * FREQ_MULT},
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{"BelowMin", 500000000 * FREQ_MULT, 600000000 * FREQ_MULT, 600000000 * FREQ_MULT},
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{"AboveMax", 1000000000 * FREQ_MULT, 900000000 * FREQ_MULT, 900000000 * FREQ_MULT},
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}
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for _, tt := range tests {
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t.Run(tt.name, func(t *testing.T) {
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got, reg := d.CalculatePLL(PLL_A, tt.freq, 0, false)
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if got < tt.wantMin || got > tt.wantMax {
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t.Errorf("CalculatePLL() = %v, want between %v and %v", got, tt.wantMin, tt.wantMax)
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}
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if reg.p1 == 0 || reg.p3 == 0 {
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t.Errorf("CalculatePLL() invalid register values: p1=%v, p2=%v, p3=%v", reg.p1, reg.p2, reg.p3)
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}
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})
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}
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}
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func TestCalculateMultisynth(t *testing.T) {
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d := &Device{}
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tests := []struct {
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name string
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freq Frequency
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pllFreq Frequency
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wantDiv bool
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}{
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{"10MHz from 800MHz", 10000000 * FREQ_MULT, 800000000 * FREQ_MULT, false},
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{"1MHz from 800MHz", 1000000 * FREQ_MULT, 800000000 * FREQ_MULT, false},
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{"Auto PLL 10MHz", 10000000 * FREQ_MULT, 0, false},
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{"150MHz DivBy4", 150000000 * FREQ_MULT, 600000000 * FREQ_MULT, true},
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{"BelowMin", 100000 * FREQ_MULT, 800000000 * FREQ_MULT, false},
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}
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for _, tt := range tests {
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t.Run(tt.name, func(t *testing.T) {
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got, reg := d.CalculateMultisynth(tt.freq, tt.pllFreq)
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if tt.pllFreq == 0 {
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// Auto mode should return a valid PLL frequency
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if got < PLL_VCO_MIN*FREQ_MULT || got > PLL_VCO_MAX*FREQ_MULT {
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t.Errorf("CalculateMultisynth() returned invalid PLL freq %v", got)
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}
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}
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if reg.p3 == 0 {
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t.Errorf("CalculateMultisynth() p3 should not be 0")
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}
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})
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}
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}
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func TestMultisynth67Calc(t *testing.T) {
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d := &Device{}
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tests := []struct {
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name string
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freq Frequency
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pllFreq Frequency
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wantErr bool
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}{
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{"10MHz Auto", 10000000 * FREQ_MULT, 0, false},
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{"100MHz Auto", 100000000 * FREQ_MULT, 0, false},
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{"100MHz from 800MHz", 100000000 * FREQ_MULT, 800000000 * FREQ_MULT, false},
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{"Invalid Division", 10000000 * FREQ_MULT, 777000000 * FREQ_MULT, true},
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}
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for _, tt := range tests {
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t.Run(tt.name, func(t *testing.T) {
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got, reg := d.multisynth67Calc(tt.freq, tt.pllFreq)
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if tt.pllFreq == 0 {
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if got < PLL_VCO_MIN*FREQ_MULT || got > PLL_VCO_MAX*FREQ_MULT {
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t.Errorf("multisynth67Calc() returned invalid PLL freq %v", got)
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}
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} else if tt.wantErr {
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if got != 0 {
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t.Errorf("multisynth67Calc() should return 0 for invalid division, got %v", got)
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}
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}
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if reg.p1 == 0 && !tt.wantErr {
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t.Errorf("multisynth67Calc() p1 should not be 0")
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}
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})
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}
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}
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func TestSetCorrection(t *testing.T) {
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// Skip this test as it requires a mock I2C bus
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t.Skip("Requires mock I2C bus implementation")
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}
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func TestSetRefFreq(t *testing.T) {
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d := &Device{}
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tests := []struct {
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name string
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freq CrystalFrequency
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wantFreq CrystalFrequency
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wantDiv uint8
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}{
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{"25MHz", 25000000, 25000000, CLKIN_DIV_1},
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{"50MHz", 50000000, 25000000, CLKIN_DIV_2},
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{"100MHz", 100000000, 25000000, CLKIN_DIV_4},
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{"30MHz", 30000000, 30000000, CLKIN_DIV_1},
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{"60MHz", 60000000, 30000000, CLKIN_DIV_2},
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}
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for _, tt := range tests {
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t.Run(tt.name, func(t *testing.T) {
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d.SetReferenceFrequency(PLLInputClockIn, tt.freq)
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if d.crystalFreq[PLLInputClockIn] != tt.wantFreq {
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t.Errorf("SetReferenceFrequency() freq = %v, want %v", d.crystalFreq[PLLInputClockIn], tt.wantFreq)
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}
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if d.clkinDiv != tt.wantDiv {
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t.Errorf("SetReferenceFrequency() clkinDiv = %v, want %v", d.clkinDiv, tt.wantDiv)
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}
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})
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}
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}
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func TestGetCorrection(t *testing.T) {
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d := &Device{}
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d.refCorrection[PLLInputXO] = 5000
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d.refCorrection[PLLInputClockIn] = -3000
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if got := d.GetCorrection(PLLInputXO); got != 5000 {
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t.Errorf("GetCorrection(PLLInputXO) = %v, want 5000", got)
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}
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if got := d.GetCorrection(PLLInputClockIn); got != -3000 {
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t.Errorf("GetCorrection(PLLInputClockIn) = %v, want -3000", got)
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}
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}
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