From 41e514150d992ae12e130c0e35408211a525756c Mon Sep 17 00:00:00 2001 From: soypat Date: Wed, 24 May 2023 20:03:35 -0300 Subject: [PATCH] add dual example --- examples/dual/dual.go | 68 ++++++++++++++++++++++++++++++ sx127x/registers.go | 33 +++++++++++++++ sx127x/regstr_string.go | 7 +++- sx127x/sx127x.go | 72 ++++++++++++++++---------------- testdata/clean1LoraRegisters.txt | 4 ++ testdata/cleanLoRaRegisters.txt | 2 + testdata/cleanLoRaRegisters2.txt | 2 + 7 files changed, 151 insertions(+), 37 deletions(-) create mode 100644 examples/dual/dual.go create mode 100644 testdata/clean1LoraRegisters.txt create mode 100644 testdata/cleanLoRaRegisters.txt create mode 100644 testdata/cleanLoRaRegisters2.txt diff --git a/examples/dual/dual.go b/examples/dual/dual.go new file mode 100644 index 0000000..7cd5ad7 --- /dev/null +++ b/examples/dual/dual.go @@ -0,0 +1,68 @@ +package main + +import ( + "fmt" + "machine" + "time" + + "github.com/soypat/lora/sx127x" +) + +const ( + pinCS0 = machine.GPIO27 + pinCS1 = machine.GPIO28 + pinRST0 = machine.GPIO29 + pinRST1 = machine.GPIO29 + pinMOSI = machine.GPIO3 + pinMISO = machine.GPIO4 + pinSCK = machine.GPIO6 +) + +var ( + dev0, dev1 *sx127x.DeviceLoRa +) + +func main() { + time.Sleep(1500 * time.Millisecond) + println("program start") + var err error + setup() + defer println("program end") + var reg, fifo [256]byte + dev0.Reset() + if !dev0.IsConnected() { + panic("not connected") + } + dev0.Write8(1, 0) + time.Sleep(100 * time.Millisecond) + // dev0.SetOpMode(sx127x.OpSleep) + err = dev0.SetOpMode(sx127x.OpSleep) + if err != nil { + panic(err.Error()) + } + time.Sleep(100 * time.Millisecond) + err = dev0.FullStatus(fifo[:], reg[:]) + if err != nil { + panic(err.Error()) + } + fmt.Printf("reg: %v\n\nfifo: %v\n", reg[:], fifo[:]) +} + +func setup() { + var bus = machine.SPI0 + err := bus.Configure(machine.SPIConfig{ + Frequency: 10_000, + SCK: pinSCK, + SDO: pinMOSI, + SDI: pinMISO, + }) + if err != nil { + panic(err.Error()) + } + pinCS0.Configure(machine.PinConfig{Mode: machine.PinOutput}) + pinCS1.Configure(machine.PinConfig{Mode: machine.PinOutput}) + pinRST0.Configure(machine.PinConfig{Mode: machine.PinOutput}) + pinRST1.Configure(machine.PinConfig{Mode: machine.PinOutput}) + dev0 = sx127x.NewLoRa(bus, pinCS0.Set, pinRST0.Set) + dev1 = sx127x.NewLoRa(bus, pinCS1.Set, pinRST1.Set) +} diff --git a/sx127x/registers.go b/sx127x/registers.go index 7517613..9489075 100644 --- a/sx127x/registers.go +++ b/sx127x/registers.go @@ -2,6 +2,7 @@ package sx127x import ( "bytes" + "errors" "fmt" "github.com/soypat/lora" @@ -297,3 +298,35 @@ func (d *DeviceLoRa) debugRegString() string { }) return buf.String() } + +func (d *DeviceLoRa) FullStatus(fifo, registers []byte) (err error) { + if len(fifo) < 256 || len(registers) < 256 { + return errors.New("fifo and registers must be at least 256 bytes long") + } + err = d.SetOpMode(OpStandby) + if err != nil { + return err + } + for addr := uint8(1); addr <= 0x4d; addr++ { + if !regstr(addr).valid() { + registers[addr] = 0 + continue // Not a readable register. + } + registers[addr], err = d.read8(addr) + if err != nil { + return err + } + } + // Read full contents of FIFO. + err = d.Write8(regFIFO_ADDR_PTR, 0) + if err != nil { + return err + } + for addr := uint8(0); addr < 255; addr++ { + fifo[addr], err = d.read8(0) + if err != nil { + return err + } + } + return nil +} diff --git a/sx127x/regstr_string.go b/sx127x/regstr_string.go index eec8e7c..30bc4cb 100644 --- a/sx127x/regstr_string.go +++ b/sx127x/regstr_string.go @@ -97,9 +97,14 @@ var __reg_map = map[regstr]string{ 77: __reg_name[507:514], } +func (i regstr) valid() bool { + _, ok := __reg_map[i] + return ok +} + func (i regstr) String() string { if str, ok := __reg_map[i]; ok { return str } - return "_reg(" + strconv.FormatInt(int64(i), 10) + ")" + return "regstr(" + strconv.FormatInt(int64(i), 10) + ")" } diff --git a/sx127x/sx127x.go b/sx127x/sx127x.go index e9c19fc..13cd3f7 100644 --- a/sx127x/sx127x.go +++ b/sx127x/sx127x.go @@ -142,7 +142,7 @@ func (d *DeviceLoRa) Configure(cfg lora.Config) (err error) { } d.Reset() // We need to be in sleep mode to set LoRa mode if in FSK/OOK. - d.write8(regOP_MODE, opmSLEEP) // No need to check error, do it in SetOpmode. + d.Write8(regOP_MODE, opmSLEEP) // No need to check error, do it in SetOpmode. if !d.IsConnected() { return ErrNotDetected } @@ -218,9 +218,9 @@ func (d *DeviceLoRa) Configure(cfg lora.Config) (err error) { if err != nil { return err } - d.write8(regFIFO_TX_BASE_ADDR, 0) - d.write8(regFIFO_RX_BASE_ADDR, 0) - d.write8(regFIFO_ADDR_PTR, 0) + d.Write8(regFIFO_TX_BASE_ADDR, 0) + d.Write8(regFIFO_RX_BASE_ADDR, 0) + d.Write8(regFIFO_ADDR_PTR, 0) d.headerType = cfg.HeaderType return d.SetOpMode(OpSleep) // Return to sleep mode to conserve power. } @@ -246,7 +246,7 @@ func (d *DeviceLoRa) IsConnected() bool { // SetOpMode sets the operating mode of the SX127x to a LoRa mode. func (d *DeviceLoRa) SetOpMode(mode OpMode) error { // We always write the LoRa mode bit - err := d.write8(regOP_MODE, byte(mode|opLoRaBit)) + err := d.Write8(regOP_MODE, byte(mode|opLoRaBit)) if err != nil { return err } @@ -319,7 +319,7 @@ func (d *DeviceLoRa) Tx(packet []byte) (err error) { return err } } - err = d.write8(regPAYLOAD_LENGTH, uint8(len(packet))) + err = d.Write8(regPAYLOAD_LENGTH, uint8(len(packet))) if err != nil { return err } @@ -336,10 +336,10 @@ func (d *DeviceLoRa) Tx(packet []byte) (err error) { if err != nil { return err } - d.write8(regFIFO_TX_BASE_ADDR, 0) - d.write8(regFIFO_ADDR_PTR, 0) + d.Write8(regFIFO_TX_BASE_ADDR, 0) + d.Write8(regFIFO_ADDR_PTR, 0) for i := 0; i < len(packet); i++ { - err := d.write8(regFIFO, packet[i]) + err := d.Write8(regFIFO, packet[i]) if err != nil { return err } @@ -373,7 +373,7 @@ func (d *DeviceLoRa) Tx(packet []byte) (err error) { // SetRxDoneOnDIO0 sets the TxDone interrupt on the DIO0 pin of the device. func (d *DeviceLoRa) SetIRQTxDoneOnDIO0() (err error) { // set the IRQ mapping DIO0=TxDone DIO1=NOP DIO2=NOP. - err = d.write8(regDIO_MAPPING_1, mapDIO0_TXDONE) + err = d.Write8(regDIO_MAPPING_1, mapDIO0_TXDONE) if err != nil { return err } @@ -388,7 +388,7 @@ func (d *DeviceLoRa) SetIRQTxDoneOnDIO0() (err error) { // SetRxDoneOnDIO0 sets the RxDone interrupt on the DIO0 pin of the device. func (d *DeviceLoRa) SetIRQRxDoneOnDIO0() (err error) { // set the IRQ mapping DIO0=TxDone DIO1=NOP DIO2=NOP. - err = d.write8(regDIO_MAPPING_1, mapDIO0_RXDONE) + err = d.Write8(regDIO_MAPPING_1, mapDIO0_RXDONE) if err != nil { return err } @@ -537,11 +537,11 @@ func (d *DeviceLoRa) prepareForRx(fifoAddr uint8) (err error) { if err != nil { return err } - err = d.write8(regFIFO_RX_BASE_ADDR, fifoAddr) + err = d.Write8(regFIFO_RX_BASE_ADDR, fifoAddr) if err != nil { return err } - return d.write8(regFIFO_ADDR_PTR, fifoAddr) + return d.Write8(regFIFO_ADDR_PTR, fifoAddr) } func (d *DeviceLoRa) gotRxContinous(fn rxCallback) error { @@ -566,7 +566,7 @@ func (d *DeviceLoRa) gotRxContinous(fn rxCallback) error { // - bit 6: Rx done interrupt // - bit 7: Rx timeout interrupt func (d *DeviceLoRa) clearIRQ(toClear uint8) error { - err := d.write8(regIRQ_FLAGS, toClear) + err := d.Write8(regIRQ_FLAGS, toClear) if err != nil { return err } @@ -722,15 +722,15 @@ func (d *DeviceLoRa) ReadConfig() (cfg lora.Config, err error) { func (d *DeviceLoRa) setPreambleLength(pLen uint16) error { var buf [2]byte binary.BigEndian.PutUint16(buf[:], pLen) - d.write8(regPREAMBLE_MSB, buf[0]) - return d.write8(regPREAMBLE_LSB, buf[1]) + d.Write8(regPREAMBLE_MSB, buf[0]) + return d.Write8(regPREAMBLE_LSB, buf[1]) } func (d *DeviceLoRa) setMaxPayloadLength(plen uint8) error { if plen == 0 { return io.ErrShortBuffer } - return d.write8(regPAYLOAD_LENGTH, plen) + return d.Write8(regPAYLOAD_LENGTH, plen) } func (d *DeviceLoRa) enableTxContinuousMode(enable bool) error { @@ -755,7 +755,7 @@ func (d *DeviceLoRa) setRFOTxPower(txPow int8) error { } MaxPower, OutputPower := rfoPowReg(txPow) // This unsets PaSelect bit which switches mode of operation to RFO pin (limited to 14dBm power). - err := d.write8(regPA_CONFIG, ((0b111&MaxPower)<<4)|(OutputPower&0b1111)) + err := d.Write8(regPA_CONFIG, ((0b111&MaxPower)<<4)|(OutputPower&0b1111)) if err != nil { return err } @@ -777,7 +777,7 @@ func (d *DeviceLoRa) setPABoostTxPower(txPow int8) error { // } outputPower := paBoostPowReg(txPow) - return d.write8(regPA_CONFIG, PASelect|MaxPower|outputPower) + return d.Write8(regPA_CONFIG, PASelect|MaxPower|outputPower) } func rfoPowReg(txPow int8) (MaxPower, OutputPower uint8) { @@ -811,7 +811,7 @@ func paBoostPowReg(txPow int8) (OutputPower uint8) { // the max current (Imax) in milliamperes. func (d *DeviceLoRa) SetOCP(mA uint8) error { const ocpEnabledMask = 1 << 5 - return d.write8(regOCP, ocpEnabledMask|(0x1F&ocpTrim(mA))) + return d.Write8(regOCP, ocpEnabledMask|(0x1F&ocpTrim(mA))) } func ocpTrim(imax uint8) uint8 { @@ -837,11 +837,11 @@ func (d *DeviceLoRa) setFrequency(freq lora.Frequency) error { freqReg[0] = byte(frf >> 16) freqReg[1] = byte(frf >> 8) freqReg[2] = byte(frf >> 0) - d.write8(regFRF_MSB, freqReg[0]) - d.write8(regFRF_MID, freqReg[1]) + d.Write8(regFRF_MSB, freqReg[0]) + d.Write8(regFRF_MID, freqReg[1]) // Note pg82: A change in the center frequency will only be taken into account when the // least significant byte FrfLsb in RegFrfLsb is written. - return d.write8(regFRF_LSB, freqReg[2]) // Write LSB last! + return d.Write8(regFRF_LSB, freqReg[2]) // Write LSB last! } // setSpreadFactorConsistent sets the spreading factor and closely related parameters @@ -862,7 +862,7 @@ func (d *DeviceLoRa) setSpreadFactorConsistent(sf lora.SpreadFactor) (err error) return err } // Set DetectionThreshold to 0x0C for SF6 and to 0x0A otherwise (SF7 to SF12). - return d.write8(regDETECTION_THRESHOLD, 0b1000|(0b10< 0 { d.debugMask[addr] = mask } @@ -957,7 +957,7 @@ func (d *DeviceLoRa) read8(addr byte) (byte, error) { return readBuf[1], err } -func (d *DeviceLoRa) write8(addr, value byte) error { +func (d *DeviceLoRa) Write8(addr, value byte) error { readBuf := make([]byte, 2) writeBuf := []byte{addr | (1 << 7), value} // set write bit. d.csEnable(true) @@ -1004,20 +1004,20 @@ func (d *DeviceLoRa) ReadTemperature() (celsius int8, err error) { // switching to FSK/OOK mode and back to LoRa mode. defer func() { // Put chip in sleep to let us switch back to LoRa mode. - d.write8(regOP_MODE, opmSLEEP) + d.Write8(regOP_MODE, opmSLEEP) time.Sleep(15 * time.Millisecond) err = d.SetOpMode(OpSleep) // Back to LoRa mode. Only error that matters. }() // Sequence taken from page 89. - d.write8(regOP_MODE, opmSLEEP) // Put chip in sleep to let us switch to FSK/OOK mode. + d.Write8(regOP_MODE, opmSLEEP) // Put chip in sleep to let us switch to FSK/OOK mode. time.Sleep(15 * time.Millisecond) - d.write8(regOP_MODE, opmSTANDBY) + d.Write8(regOP_MODE, opmSTANDBY) time.Sleep(1000 * time.Microsecond) // Wait for oscillator startup. - d.write8(regOP_MODE, opmFSRX) + d.Write8(regOP_MODE, opmFSRX) d.writeMasked8(regImageCal, 1, 0) // Set TempMonitorOff = 0 (enables the sensor). It is not required to wait for the PLL Lock indication time.Sleep(140 * time.Microsecond) d.writeMasked8(regImageCal, 1, 1) // Set TempMonitorOff = 1 (disables the sensor). - d.write8(regOP_MODE, opmSLEEP) + d.Write8(regOP_MODE, opmSLEEP) value, _ := d.read8(regTemp) // Following calculation maps value = 255 - 2*(value-64) @@ -1028,7 +1028,7 @@ func (d *DeviceLoRa) readerToLastPacket() (_ *fifoReader, err error) { // IRQ check according to page 41 of the datasheet. // Flags must not be asserted in order to ensure packet reception has terminated succesfully. const mustBeUnset = irqRXDONE_MASK | irqHEADER_MASK | irqCRCERR_MASK | irqTXDONE_MASK - d.write8(regIRQ_FLAGS, mustBeUnset) + d.Write8(regIRQ_FLAGS, mustBeUnset) var irqFlags uint8 for count := 0; count < 100; count++ { irqFlags, err = d.read8(regIRQ_FLAGS) @@ -1056,7 +1056,7 @@ func (d *DeviceLoRa) readerToLastPacket() (_ *fifoReader, err error) { if numBytes == 0 { return nil, errors.New("readerToNextPacket called with RX_NB_BYTES=0") } - err = d.write8(regFIFO_ADDR_PTR, curraddr) + err = d.Write8(regFIFO_ADDR_PTR, curraddr) if err != nil { return nil, err } diff --git a/testdata/clean1LoraRegisters.txt b/testdata/clean1LoraRegisters.txt new file mode 100644 index 0000000..a5525eb --- /dev/null +++ b/testdata/clean1LoraRegisters.txt @@ -0,0 +1,4 @@ +reg: [0 129 0 0 0 0 108 128 0 79 9 43 32 0 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 114 112 100 0 8 1 255 0 0 4 0 0 0 0 0 0 0 0 0 0 195 0 39 0 0 0 10 0 18 0 29 0 0 0 0 0 0 18 0 0 0 0 0 0 0 0 0 0 132 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0] +fifo: [38 100 45 213 64 144 67 9 146 180 160 199 24 18 194 52 176 73 80 6 114 169 64 74 94 114 154 189 12 156 42 104 135 65 69 40 37 2 218 158 37 80 131 129 200 214 8 32 87 10 33 121 209 200 29 10 129 245 10 18 4 67 81 20 42 248 73 172 168 237 168 66 84 109 204 182 51 95 57 213 26 9 131 70 96 238 53 92 33 66 5 4 79 136 230 0 137 164 8 254 1 91 64 48 146 43 93 184 146 36 41 18 160 168 92 188 144 131 2 193 69 1 130 147 10 24 210 60 114 119 91 215 59 217 171 159 35 49 21 89 36 47 251 0 95 94 109 102 158 93 91 229 54 22 55 239 27 149 141 151 254 165 161 55 169 244 203 114 205 36 95 216 100 159 115 187 48 205 28 141 70 198 87 2 188 87 47 210 243 161 207 199 122 209 206 107 90 239 55 188 205 186 239 66 63 83 102 127 117 207 246 183 236 135 254 223 27 255 197 219 154 142 24 188 149 156 19 154 96 63 230 227 190 85 7 95 237 173 237 93 205 165 133 44 171 138 169 121 109 126 175 247 234 200 240 0] +reg: [0 129 0 0 0 0 108 128 0 79 9 43 32 0 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 114 112 100 0 8 1 255 0 0 4 0 0 0 0 0 0 0 0 0 0 195 0 39 0 0 0 10 0 18 0 29 0 0 0 0 0 0 18 0 0 0 0 0 0 0 0 0 0 132 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0] +fifo: [38 100 45 197 64 144 67 25 146 132 160 71 24 18 194 52 48 73 85 6 112 169 64 66 78 114 154 157 12 140 34 104 135 65 71 40 53 2 218 158 33 80 131 129 202 214 8 48 87 10 33 121 145 204 28 10 129 245 74 0 4 67 81 20 42 248 73 172 160 205 168 70 84 101 204 182 51 31 57 213 90 9 131 70 96 172 53 92 33 66 5 4 15 136 230 1 137 164 8 254 129 75 64 48 146 43 93 184 146 36 41 16 160 136 92 184 144 131 2 192 69 1 130 147 10 24 210 52 114 119 27 215 59 217 171 155 35 49 21 85 60 47 251 0 95 94 109 126 158 93 90 229 118 22 55 239 27 149 143 151 254 165 33 55 169 244 203 114 237 36 95 220 100 159 115 191 48 201 28 141 70 198 87 2 188 87 47 210 243 161 207 199 122 209 206 107 90 239 63 188 197 186 239 66 63 83 78 255 244 207 214 183 204 135 254 223 27 253 69 211 154 158 24 188 149 156 23 218 224 63 166 227 190 85 7 95 237 173 173 93 205 181 133 125 171 138 233 123 109 126 175 247 234 232 112 0] \ No newline at end of file diff --git a/testdata/cleanLoRaRegisters.txt b/testdata/cleanLoRaRegisters.txt new file mode 100644 index 0000000..57a64d9 --- /dev/null +++ b/testdata/cleanLoRaRegisters.txt @@ -0,0 +1,2 @@ +reg: [0 129 26 11 0 91 108 208 17 79 9 43 32 0 128 0 0 0 0 0 0 0 0 0 16 0 0 0 0 114 112 100 0 8 1 255 0 0 4 0 0 0 0 0 0 80 20 69 85 195 5 39 28 10 3 10 66 18 82 29 0 175 0 0 0 0 18 36 45 0 3 0 4 35 0 9 5 132 50 43 20 0 0 14 0 0 0 15 224 0 12 240 8 0 92 120 0 28 14 91 204 0 1 80 0 0 0 0 0 0 0 11 208 0 20 0 0 0 0 0 0 0 0 0 0 0 0 0 163 129 26 11 0 82 108 128 0 79 9 43 32 1 128 0 0 0 0 0 0 0 0 0 16 0 0 0 0 114 112 100 0 8 1 255 0 0 4 0 0 0 0 0 0 80 20 69 85 195 5 39 28 10 3 10 66 18 82 29 0 175 0 0 0 0 18 36 45 0 3 0 4 35 0 9 5 132 50 43 20 0 0 14 0 0 0 15 224 0 12 240 8 0 92 120 0 28 14 91 204 0 1 80 0 0 0 0 0 0 0 11 208 0 20 0 0 0 0 0 0 0 0 0 0 0 0 0] +fifo: [163 212 34 103 43 163 162 194 15 31 155 17 44 8 136 1 152 66 0 204 205 45 52 129 55 232 38 2 233 0 205 141 138 194 211 72 34 254 80 131 164 179 98 177 25 17 250 209 170 176 18 11 137 101 233 32 88 96 9 232 169 42 244 236 176 88 48 20 199 144 21 192 39 113 15 249 24 16 23 41 198 225 128 216 50 233 197 76 64 16 32 227 218 124 59 69 144 89 90 50 228 225 29 26 156 138 51 2 132 165 236 186 238 70 142 162 30 68 168 217 242 217 100 247 126 118 145 53 154 6 109 219 144 196 139 217 243 4 138 90 123 236 233 35 254 117 108 247 185 70 126 20 175 41 110 213 61 158 226 249 154 61 252 175 179 83 39 10 25 223 75 103 166 179 39 73 223 24 148 53 225 233 251 150 214 66 158 31 175 165 23 205 246 181 140 229 125 189 47 205 30 252 150 233 93 121 115 103 180 171 122 206 54 130 234 217 156 123 137 182 4 194 213 239 206 175 189 123 133 77 38 202 83 61 158 178 66 209 210 0 180 70 231 101 62 53 81 30 170 244 237 216 82 80 195 0] \ No newline at end of file diff --git a/testdata/cleanLoRaRegisters2.txt b/testdata/cleanLoRaRegisters2.txt new file mode 100644 index 0000000..7e0d0f9 --- /dev/null +++ b/testdata/cleanLoRaRegisters2.txt @@ -0,0 +1,2 @@ +reg: [0 129 18 10 21 0 148 72 144 72 9 42 32 2 0 0 36 10 5 5 0 0 0 0 10 5 0 0 5 0 130 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 128 64 20 137 18 10 1 1 1 0 0 0 1 0 8 0 128 64 0 0 1 0 0 0 128 64 0 0 128 9 128 64 168 32 69 9 164 82 164 82 82 41 0 0 0 0 0 0 128 64 0 82 0 41 128 0 64 32 0 41 64 64 41 32 148 32 36 129 132 10 0 82 72 128 0 128 9 42 32 9 0 0 65 0 0 0 0 0 0 0 16 0 0 0 0 66 64 68 40 137 0 64 64 64 0 0 0 0 0 0 0 128 128 42 32 0 72 72 0 9 0 42 16 72 0 0 72 128 128 64 0 129 18 0 0 132 0 0 0 0 9 42 0 0 72 0 0 0 0 66 0 0 0 0 16 0 0 0 0 128 128 66 64 32 128 16 0 132 0 0 0 128 128 0 33 128 132 66 132 16 64 64 72 0 0 72 66 64 72 0 33 160 144 0] +fifo: [36 16 64 64 64 64 34 41 8 0 0 0 0 68 2 16 66 16 72 10 41 68 64 0 0 0 0 0 1 36 16 0 0 0 64 72 36 4 18 0 0 0 0 0 0 0 0 18 18 21 9 36 64 0 0 0 66 72 34 32 0 0 0 0 0 0 8 34 73 68 66 66 17 0 0 0 0 0 0 64 16 5 2 20 64 64 0 0 0 0 18 10 18 69 18 32 0 64 64 17 82 66 9 17 82 42 9 17 144 64 0 0 16 64 80 34 0 0 0 0 0 0 65 20 9 32 21 32 34 84 81 16 2 0 0 0 0 0 0 16 16 81 20 41 9 8 0 0 0 0 0 0 0 0 0 36 66 18 10 0 0 0 0 18 72 80 136 0 0 0 0 64 136 17 32 74 36 73 17 0 0 0 0 0 74 69 64 81 80 34 0 0 0 1 2 65 64 0 0 0 2 0 9 144 40 18 0 0 0 0 0 2 64 2 9 74 33 65 16 32 0 0 0 64 17 68 17 4 64 16 68 81 2 5 36 0 0 0 0 0 64 36 4 32 68 65 32 136 74 18 34 73 4 0 0 0] \ No newline at end of file