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https://github.com/portapack-mayhem/mayhem-firmware.git
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stafur
39424632bb
* Initial commit and pr for HackRF Pro (praline) arch-port to mayhem-firmware. Please see https://github.com/portapack-mayhem/mayhem-firmware/issues/2957. Added flash specifics for -DBOARD=PRALINE. This firmware only builds with toolchain v9.2.1 if hackrf codebase has -B arm in firmware/hackrf_usb/CMakeLists.txt. * Updated CMakeLists.txt per coordination with @HtoToo. For -DBOARD=PRALINE FLASH_MB_SIZE and FLASH_MB_LIMIT_SIZE are now 4. Removed praline specific variable for FLASH limits. * Updated chibios-portapack's board.cpp to support initialization of the HachRF-Pro (praline) FPGA. Added append_fpga_bitstream.py tool to ensure that praline_fgpa.bin bitstream can be appended to -DBOARD=PRALINE produced firmware. In order to ensure successful execution of append_fpga_bitstream.py to append the fpga bitstream we should expect that the bistsream will be located at 0x180000 in flash. This requires that FLASH_MB_LIMIT_SIZE must be 1.5, and FLASH_BYTES_LIMIT_SIZE must be 1535 * 1024. If we want to allow more or less space for the base firmware image sans the fpga bitstream the location of the bistream must be moved to a location other than 0x180000. * Updated location of praline_fpga.bin bitstream to 0x380000 to allow more room for firmware. Firmware now has 3.5MB, or 2MB more available than before as coordinated with @HTotoo. * Expanded #ifndef PRALINE to include og and r9 gpio and pin setup as coordinated with @HTotoo. * Added note for PRALINE FLASH_MB_LIMIT_SIZE and FLASH_BYTES_LIMIT_SIZE to explain why we are using the 3.5 and 3584 values respectively as coordinated with @HTotoo. * Next round of modifications derived heavily, if not entirely from work done by @banandana at https://github.com/Banandana/mayhem-firmware. This commit should power on the HackRF Pro (praline) display, power on the fpga, and enable gpio, and provide debug utilties. There is still a lot of work to be done to fully enable the new praline board with this build and firmware architectural porting effort. However, hackrf-one boards do not seem to be adversely impacted by the #ifdef PRALINE statements, and CMakeLists updates, as far as I have been able to test. * Ran format-code.sh. Updates for this commit are only due to formatting. Tested builds and they seem to work as exptected. * Addressed fixes in firmware/application and firmware/baseband. Stream now flows to capture and looking glass. Issues were related to thread management. Issues were originally addressed by @banandana. * Ran format-code.sh to allow for consistency with autoamted clang checks. * Update hackrf ref repo to mayhem-portapack-hackrf next from https://github.com/portapack-mayhem/hackrf * Addressed format edits necessary to pass clang-format check. * Starting addressing Si5351 Clocks for radio sampling. These updates correctly set the Si5351 clock at start up. There appears to be an issue during runtime when testing with RX Test Init, Capture and Looking glass. * Updated clock_manager.cpp to restore correct function introduced by @banandana when testing with Rx Test Init. * Switched to using decimation for setting the sample rate without changing the Si5351 clock. This assumes that for the praline board Si5351 CLK0 runs at fixed 8 MHz (constant) and the FPGA decimates to get the desired sample rate. For example, for a 1 MHz sample rate -> Si5351 outputs 8 MHz, FPGA decimates by 8. There is still more work needed here, and potential verification that this is the correct way to operate with this new archteitecture. * After deliberating on hackrf_usb hackrf_core.c and radio.c, and reviewing firmware/application/hw/si5351.cpp the original approach of using the aproach detailed in hackrf_core.c sample_rate_frac_set() lines 580-582, via the implementation in firmware/application/hw/si5351.cpp seems like the best place to continue testing efforts. * Tested at ~2.4GHz (2.3 - 2.5) with lookgin glass and was able to receive signals. Added a Signal Path debug app to test gains, and readio mode (receive/transmit). * Added two debug apps for the RFFC507x. Status View and Tuning View. This helped debug some of the potential issues with tuning. * update submodule * format code * Small touch up merging latest next and ensuring build for HackRF One. * Reverted edits to re: firmware/baseband/sd_over_usb/scsi.c and firmware/application/portapack.cpp. Source now builds, had to pull latest hackrf submodule. * Skipped detect hardware for praline board to avoid backscreen in HackRF Pro praline board. --------- Co-authored-by: gullradriel <gullradriel@users.noreply.github.com>
167 lines
6.1 KiB
C++
167 lines
6.1 KiB
C++
/*
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* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __HACKRF_GPIO_H__
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#define __HACKRF_GPIO_H__
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#include "pins.hpp"
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#include "led.hpp"
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#include <array>
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using namespace lpc43xx;
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namespace hackrf {
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namespace one {
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/* GPIO */
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constexpr GPIO gpio_led_usb = gpio[GPIO2_1];
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constexpr GPIO gpio_led_rx = gpio[GPIO2_2];
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constexpr GPIO gpio_led_tx = gpio[GPIO2_8];
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constexpr GPIO gpio_og_1v8_enable = gpio[GPIO3_6];
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constexpr GPIO gpio_r9_1v8_enable = gpio[GPIO2_9];
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constexpr GPIO gpio_vregmode = gpio[GPIO3_7];
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#ifdef PRALINE
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// PRALINE uses different power control pins
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constexpr GPIO gpio_og_vaa_disable = gpio[GPIO4_1]; // PRALINE VAA disable (P8_1)
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constexpr GPIO gpio_r9_vaa_disable = gpio[GPIO4_1]; // PRALINE VAA disable (P8_1)
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#else
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constexpr GPIO gpio_og_vaa_disable = gpio[GPIO2_9];
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constexpr GPIO gpio_r9_vaa_disable = gpio[GPIO3_6];
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#endif
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constexpr GPIO gpio_rx_mix_bp = gpio[GPIO2_12];
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constexpr GPIO gpio_tx_mix_bp = gpio[GPIO2_11];
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constexpr GPIO gpio_mix_bypass = gpio[GPIO5_16];
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constexpr GPIO gpio_not_mix_bypass = gpio[GPIO1_0];
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constexpr GPIO gpio_og_rx = gpio[GPIO5_5];
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constexpr GPIO gpio_og_tx = gpio[GPIO5_15];
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constexpr GPIO gpio_r9_rx = gpio[GPIO0_7];
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constexpr GPIO gpio_lp = gpio[GPIO2_10];
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constexpr GPIO gpio_hp = gpio[GPIO2_0];
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constexpr GPIO gpio_rx_amp = gpio[GPIO1_11];
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constexpr GPIO gpio_tx_amp = gpio[GPIO2_15];
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constexpr GPIO gpio_amp_bypass = gpio[GPIO0_14];
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constexpr GPIO gpio_not_rx_amp_pwr = gpio[GPIO1_12];
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constexpr GPIO gpio_not_tx_amp_pwr = gpio[GPIO3_5];
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constexpr GPIO gpio_rffc5072_resetx = gpio[GPIO2_14];
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constexpr GPIO gpio_rffc5072_select = gpio[GPIO2_13];
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#ifdef PRALINE
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constexpr GPIO gpio_rffc5072_clock = gpio[GPIO5_18];
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constexpr GPIO gpio_rffc5072_data = gpio[GPIO4_14];
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#else
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constexpr GPIO gpio_rffc5072_clock = gpio[GPIO5_6];
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constexpr GPIO gpio_rffc5072_data = gpio[GPIO3_3];
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#endif
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#ifdef PRALINE
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constexpr GPIO gpio_max283x_select = gpio[GPIO6_28];
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#else
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constexpr GPIO gpio_max283x_select = gpio[GPIO0_15];
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#endif
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#ifdef PRALINE
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// PRALINE uses MAX2831 transceiver with different control pins
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constexpr GPIO gpio_max283x_enable = gpio[GPIO7_1]; // MAX2831 ENABLE (PE_1)
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constexpr GPIO gpio_max2831_enable = gpio[GPIO7_1]; // Alias
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constexpr GPIO gpio_max2831_rx_enable = gpio[GPIO7_2]; // MAX2831 RX_ENABLE (PE_2)
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constexpr GPIO gpio_max2831_rxhp = gpio[GPIO6_29]; // MAX2831 RXHP (PD_15)
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constexpr GPIO gpio_max2831_ld = gpio[GPIO4_11]; // MAX2831 Lock Detect (P9_6)
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// Legacy aliases for code compatibility
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constexpr GPIO gpio_max2837_rxenable = gpio[GPIO7_2];
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constexpr GPIO gpio_max2837_txenable = gpio[GPIO7_2]; // MAX2831 uses single RX/TX control
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constexpr GPIO gpio_max2839_rxtx = gpio[GPIO7_2];
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#else
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constexpr GPIO gpio_max283x_enable = gpio[GPIO2_6];
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constexpr GPIO gpio_max2837_rxenable = gpio[GPIO2_5];
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constexpr GPIO gpio_max2837_txenable = gpio[GPIO2_4];
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constexpr GPIO gpio_max2839_rxtx = gpio[GPIO2_5];
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#endif
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#ifdef PRALINE
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constexpr GPIO gpio_max5864_select = gpio[GPIO6_30];
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constexpr GPIO gpio_fpga_select = gpio[GPIO2_10]; // FPGA SPI CS (P5_1)
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#else
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constexpr GPIO gpio_max5864_select = gpio[GPIO2_7];
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#endif
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constexpr GPIO gpio_q_invert = gpio[GPIO0_13];
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#ifdef PRALINE
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// PRALINE power control
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constexpr GPIO gpio_vaa_disable = gpio[GPIO4_1]; // VAA disable (P8_1)
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constexpr GPIO gpio_1v2_enable = gpio[GPIO4_7]; // 1V2 enable (P8_7)
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constexpr GPIO gpio_3v3aux_disable = gpio[GPIO5_15]; // 3V3 aux disable (P6_7)
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// PRALINE RF path control
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constexpr GPIO gpio_tx_enable = gpio[GPIO3_4]; // TX enable (P6_5)
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constexpr GPIO gpio_mix_enable_n = gpio[GPIO3_2]; // Mixer enable inverted (P6_3)
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constexpr GPIO gpio_lpf_enable = gpio[GPIO4_8]; // LPF enable (PA_1)
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constexpr GPIO gpio_rf_amp_enable = gpio[GPIO4_9]; // RF amp enable (PA_2)
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constexpr GPIO gpio_ant_bias_disable = gpio[GPIO1_12]; // Antenna bias disable (P2_12)
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// PRALINE mixer lock detect (gpio_max2831_ld defined above at line 93)
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constexpr GPIO gpio_rffc5072_ld = gpio[GPIO6_25]; // Mixer lock detect (PD_11)
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// PRALINE LED4
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constexpr GPIO gpio_led4 = gpio[GPIO4_6]; // LED4 (P8_6)
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// PRALINE dual port control
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constexpr GPIO gpio_p1_ctrl0 = gpio[GPIO0_14]; // P1 control 0 (P2_10)
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constexpr GPIO gpio_p1_ctrl1 = gpio[GPIO5_16]; // P1 control 1 (P6_8)
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constexpr GPIO gpio_p1_ctrl2 = gpio[GPIO3_5]; // P1 control 2 (P6_9)
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constexpr GPIO gpio_p2_ctrl0 = gpio[GPIO7_3]; // P2 control 0 (PE_3)
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constexpr GPIO gpio_p2_ctrl1 = gpio[GPIO7_4]; // P2 control 1 (PE_4)
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constexpr GPIO gpio_clkin_ctrl = gpio[GPIO0_15]; // CLKIN control (P1_20)
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// PRALINE trigger/sync I/O
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constexpr GPIO gpio_trigger_in = gpio[GPIO6_26]; // Trigger input (PD_12)
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constexpr GPIO gpio_trigger_out = gpio[GPIO5_6]; // Trigger output (P2_6)
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constexpr GPIO gpio_pps_out = gpio[GPIO5_5]; // PPS output (P2_5)
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#endif
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constexpr GPIO gpio_cpld_tdo = gpio[GPIO5_18];
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constexpr GPIO gpio_cpld_tck = gpio[GPIO3_0];
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constexpr GPIO gpio_cpld_tms = gpio[GPIO3_4];
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constexpr GPIO gpio_cpld_tdi = gpio[GPIO3_1];
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constexpr GPIO gpio_r9_clkin_en = gpio[GPIO5_15];
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constexpr GPIO gpio_r9_clkout_en = gpio[GPIO0_9];
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constexpr GPIO gpio_r9_mcu_clk_en = gpio[GPIO0_8];
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constexpr GPIO gpio_r9_not_ant_pwr = gpio[GPIO2_4];
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/* LEDs */
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constexpr LED led_usb{gpio_led_usb};
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constexpr LED led_rx{gpio_led_rx};
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constexpr LED led_tx{gpio_led_tx};
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} /* namespace one */
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} /* namespace hackrf */
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#endif /*__HACKRF_GPIO_H__*/
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