mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-08-19 14:14:04 +00:00
Pezsma
2ad34bbc09
* Refactor GPIO mappings and definitions for improved clarity and functionality - Updated SCU_ARRAY_SIZE definitions in pal_lld.h for PRALINE and non-PRALINE configurations. - Modified pin mappings in gpio.hpp to reflect new hardware configurations, including additional control pins for RF and audio components. - Removed obsolete GPIO definitions from hackrf_gpio.hpp and streamlined the code for better maintainability. - Added new GPIO definitions for mix bypass, amplifier control, and other RF-related functionalities to enhance the system's capabilities. * Refactor GPIO mappings and update SCU_ARRAY_SIZE for LPC43xx platform - Updated SCU_ARRAY_SIZE to 80 for PRALINE configuration and 58 for others. - Added new GPIO mappings for auxiliary power control, antenna bias, and R9 clock enable signals in gpio.hpp. - Removed commented-out PPS output mapping in hackrf_gpio.hpp. - Adjusted GPIO definitions for R9 clock signals to ensure proper functionality. * Refactor RF path initialization and configuration for improved clarity and functionality * Refactor RF path configuration and GPIO mappings for improved clarity and functionality * Potential fix for pull request finding * comment * aux power polarrity * Fix formatting of pin_aux_power_enable declaration
692 lines
32 KiB
C++
692 lines
32 KiB
C++
/*
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* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __GPIO_H__
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#define __GPIO_H__
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#include <array>
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#include <cstddef>
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#include <cstdint>
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#include "ch.h"
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#include "hal.h"
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#include "pal_lld.h"
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struct PinConfig {
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const uint32_t mode;
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const uint32_t pd;
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const uint32_t pu;
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const uint32_t fast;
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const uint32_t input;
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const uint32_t ifilt;
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constexpr operator uint16_t() const {
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return (((~ifilt) & 1) << 7) | ((input & 1) << 6) | ((fast & 1) << 5) | (((~pu) & 1) << 4) | ((pd & 1) << 3) | ((mode & 7) << 0);
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}
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/*
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constexpr operator uint32_t() {
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return scu::sfs::mode::value(mode)
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<< scu::sfs::epd::value(pd)
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<< scu::sfs::epun::value(~pu)
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<< scu::sfs::ehs::value(fast)
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<< scu::sfs::ezi::value(input)
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<< scu::sfs::zif::value(~ifilt)
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;
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}
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*/
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static constexpr PinConfig reset() {
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return {.mode = 0, .pd = 0, .pu = 1, .fast = 0, .input = 0, .ifilt = 1};
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}
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static constexpr PinConfig floating(
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const uint32_t mode) {
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return {
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.mode = mode,
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.pd = 0,
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.pu = 0,
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.fast = 0,
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.input = 0,
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.ifilt = 1};
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}
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static constexpr PinConfig floating_input(
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const uint32_t mode) {
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return {
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.mode = mode,
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.pd = 0,
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.pu = 0,
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.fast = 0,
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.input = 1,
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.ifilt = 1};
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}
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static constexpr PinConfig floating_input_with_pull(
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const uint32_t pull_direction,
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const uint32_t mode) {
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return {
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.mode = mode,
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.pd = (pull_direction == 0) ? 1U : 0U,
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.pu = (pull_direction == 1) ? 1U : 0U,
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.fast = 0,
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.input = 1,
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.ifilt = 1};
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}
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static constexpr PinConfig gpio_led(const uint32_t mode) {
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return {.mode = mode, .pd = 0, .pu = 0, .fast = 0, .input = 0, .ifilt = 1};
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}
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static constexpr PinConfig gpio_inout_with_pull(
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const uint32_t mode,
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const uint32_t pull_direction) {
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return {
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.mode = mode,
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.pd = (pull_direction == 0) ? 1U : 0U,
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.pu = (pull_direction == 1) ? 1U : 0U,
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.fast = 0,
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.input = 1,
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.ifilt = 1};
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}
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static constexpr PinConfig gpio_inout_with_pullup(const uint32_t mode) {
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return gpio_inout_with_pull(mode, 1);
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}
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static constexpr PinConfig gpio_inout_with_pulldown(const uint32_t mode) {
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return gpio_inout_with_pull(mode, 0);
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}
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static constexpr PinConfig gpio_out_with_pull(
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const uint32_t mode,
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const uint32_t pull_direction) {
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return {
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.mode = mode,
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.pd = (pull_direction == 0) ? 1U : 0U,
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.pu = (pull_direction == 1) ? 1U : 0U,
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.fast = 0,
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.input = 0,
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.ifilt = 1};
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}
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static constexpr PinConfig gpio_out_with_pulldown(const uint32_t mode) {
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return gpio_out_with_pull(mode, 0);
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}
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static constexpr PinConfig gpio_out_with_pullup(const uint32_t mode) {
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return gpio_out_with_pull(mode, 1);
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}
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static constexpr PinConfig sgpio_in_fast(const uint32_t mode) {
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return {.mode = mode, .pd = 0, .pu = 0, .fast = 0, .input = 1, .ifilt = 0};
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}
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static constexpr PinConfig sgpio_out_fast_with_pull(
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const uint32_t mode,
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const uint32_t pull_direction) {
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return {
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.mode = mode,
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.pd = (pull_direction == 0) ? 1U : 0U,
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.pu = (pull_direction == 1) ? 1U : 0U,
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.fast = 1,
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.input = 0,
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.ifilt = 1};
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}
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static constexpr PinConfig sgpio_out_fast_with_pullup(const uint32_t mode) {
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return sgpio_out_fast_with_pull(mode, 1);
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}
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static constexpr PinConfig sgpio_inout_fast(const uint32_t mode) {
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return {.mode = mode, .pd = 0, .pu = 0, .fast = 1, .input = 1, .ifilt = 0};
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}
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static constexpr PinConfig i2c(const uint32_t mode) {
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return {.mode = mode, .pd = 0, .pu = 0, .fast = 0, .input = 1, .ifilt = 1};
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}
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static constexpr PinConfig spifi_sck(const uint32_t mode) {
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return {.mode = mode, .pd = 0, .pu = 0, .fast = 1, .input = 1, .ifilt = 0};
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}
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static constexpr PinConfig spifi_inout(const uint32_t mode) {
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return {.mode = mode, .pd = 0, .pu = 0, .fast = 1, .input = 1, .ifilt = 0};
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}
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static constexpr PinConfig spifi_cs(const uint32_t mode) {
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return {.mode = mode, .pd = 0, .pu = 0, .fast = 1, .input = 1, .ifilt = 0};
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}
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};
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struct Pin {
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// Pin() = delete;
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// Pin(const Pin&) = delete;
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// Pin(Pin&&) = delete;
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constexpr Pin(
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const uint8_t port,
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const uint8_t pad)
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: _pin_port{port},
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_pin_pad{pad} {
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}
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void mode(const uint_fast16_t mode) const {
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LPC_SCU->SFSP[_pin_port][_pin_pad] =
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(LPC_SCU->SFSP[_pin_port][_pin_pad] & 0xfffffff8) | mode;
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}
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void configure(const PinConfig config) const {
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LPC_SCU->SFSP[_pin_port][_pin_pad] = config;
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}
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uint8_t _pin_port;
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uint8_t _pin_pad;
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};
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// Defines the logical polarity of the GPIO pin
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enum class Polarity {
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ActiveHigh, // High physical state means the function is ON (default)
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ActiveLow // Low physical state means the function is ON (inverted)
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};
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struct GPIO {
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// GPIO() = delete;
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// GPIO(const GPIO& gpio) = delete;
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// GPIO(GPIO&&) = delete;
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constexpr GPIO(
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const Pin& pin,
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const ioportid_t gpio_port,
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const iopadid_t gpio_pad,
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const uint16_t gpio_mode,
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const Polarity polarity = Polarity::ActiveHigh) // Default parameter ensures backward compatibility
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: _pin{pin},
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_gpio_port{gpio_port},
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_gpio_pad{gpio_pad},
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_gpio_mode{gpio_mode},
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_polarity{polarity} {
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}
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constexpr ioportid_t port() const {
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return _gpio_port;
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}
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constexpr iopadid_t pad() const {
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return _gpio_pad;
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}
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constexpr Pin pin() const {
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return _pin;
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}
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// Returns the configured polarity of the pin
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constexpr Polarity polarity() const {
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return _polarity;
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}
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void configure() const {
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_pin.mode(_gpio_mode);
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}
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uint_fast16_t mode() const {
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return _gpio_mode;
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}
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// Physical Level Operations
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void set() const {
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palSetPad(_gpio_port, _gpio_pad);
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}
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void clear() const {
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palClearPad(_gpio_port, _gpio_pad);
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}
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void toggle() const {
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palTogglePad(_gpio_port, _gpio_pad);
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}
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void output() const {
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palSetPadMode(_gpio_port, _gpio_pad, PAL_MODE_OUTPUT_PUSHPULL);
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}
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void input() const {
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palSetPadMode(_gpio_port, _gpio_pad, PAL_MODE_INPUT);
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}
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void write(const bool value) const {
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palWritePad(_gpio_port, _gpio_pad, value);
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}
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bool read() const {
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return palReadPad(_gpio_port, _gpio_pad);
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}
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// Turns the feature ON based on its polarity
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void setActive() const {
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if (_polarity == Polarity::ActiveHigh) {
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set();
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} else {
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clear();
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}
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}
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// Turns the feature OFF based on its polarity
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void setInactive() const {
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if (_polarity == Polarity::ActiveHigh) {
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clear();
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} else {
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set();
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}
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}
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// Sets the logical state of the feature
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void setState(const bool active) const {
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if (active) {
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setActive();
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} else {
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setInactive();
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}
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}
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// Returns true if the feature is logically active/enabled
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bool isEnabled() const {
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const bool physical_state = read();
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return (_polarity == Polarity::ActiveHigh) ? physical_state : !physical_state;
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}
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bool operator!=(const GPIO& other) const {
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return (port() != other.port()) || (pad() != other.pad());
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}
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const Pin _pin;
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const ioportid_t _gpio_port;
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const iopadid_t _gpio_pad;
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const uint16_t _gpio_mode;
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const Polarity _polarity;
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};
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constexpr uint32_t boot_bit(const GPIO& pin, bool state) {
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return (state ? 1UL : 0UL) << pin.pad();
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}
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inline void setup_pin(const scu_setup_t& pin_setup) {
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LPC_SCU->SFSP[pin_setup.port][pin_setup.pin] = pin_setup.config;
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}
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template <size_t N>
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inline void setup_gpios(const std::array<gpio_setup_t, N>& pins_setup) {
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for (size_t i = 0; i < N; i++) {
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LPC_GPIO->PIN[i] |= pins_setup[i].data;
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LPC_GPIO->DIR[i] |= pins_setup[i].dir;
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}
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}
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template <size_t N>
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inline void setup_pins(const std::array<scu_setup_t, N>& pins_setup) {
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for (const auto& pin_setup : pins_setup) {
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setup_pin(pin_setup);
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}
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}
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namespace gpio_control {
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struct PinMap {
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uint8_t scu_port;
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uint8_t scu_pin;
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uint8_t gpio_port;
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uint8_t gpio_pad;
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uint8_t gpio_mode;
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};
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#ifdef PRALINE
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constexpr PinMap map_p1_ctrl0{2, 10, 0, 14, 0}; // SCU: 2, 10 | GPIO: 0, 14
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constexpr PinMap map_p1_ctrl1{6, 8, 5, 16, 4};
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constexpr PinMap map_p1_ctrl2{6, 9, 3, 5, 0};
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constexpr PinMap map_p2_ctrl0{14, 3, 7, 3, 0};
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constexpr PinMap map_p2_ctrl1{14, 4, 7, 4, 0};
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constexpr PinMap map_trigger_out{2, 6, 5, 6, 4};
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constexpr PinMap map_trigger_in{13, 12, 6, 26, 4};
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constexpr PinMap map_clkin_ctrl{1, 20, 0, 15, 0};
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constexpr PinMap map_rf5072_mix_en{9, 0, 4, 12, 0};
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constexpr PinMap map_aa_en{1, 14, 1, 7, 0}; // Anti-Aliasing filter
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constexpr PinMap map_sgpio_4{9, 4, 5, 17, 6};
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constexpr PinMap map_sgpio_8{8, 0, 4, 0, 4};
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constexpr PinMap map_sgpio_9{9, 3, 4, 15, 6};
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constexpr PinMap map_sgpio_10{8, 2, 4, 2, 4};
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constexpr PinMap map_vregmode{4, 9, 5, 13, 4};
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constexpr PinMap map_en_1v2{8, 7, 4, 7, 0};
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constexpr PinMap map_VAA_en{8, 1, 4, 1, 0};
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constexpr PinMap map_aux_power_enable{6, 7, 5, 15, 4};
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constexpr PinMap map_ant_bias{2, 12, 1, 12, 0};
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constexpr PinMap map_ant_bias_oc{2, 11, 1, 11, 0};
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constexpr PinMap map_aux_power_oc{6, 11, 3, 7, 0};
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constexpr PinMap map_led_mcu{8, 6, 4, 6, 0};
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constexpr PinMap map_mix_bypass{6, 3, 3, 2, 0};
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constexpr PinMap map_lpf{10, 1, 4, 8, 4};
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constexpr PinMap map_tx_enable{6, 5, 3, 4, 0};
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constexpr PinMap map_rf_amp_enable{10, 2, 4, 9, 0};
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constexpr PinMap map_pps_in_out{2, 5, 5, 5, 4};
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// constexpr PinMap map_unused_1{2, 7, 0, 7, 0};
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#else
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constexpr PinMap map_sgpio_4{6, 3, 3, 2, 2};
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constexpr PinMap map_sgpio_8{9, 6, 4, 11, 6};
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constexpr PinMap map_sgpio_9{4, 3, 2, 3, 7};
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constexpr PinMap map_sgpio_10{1, 14, 1, 7, 6};
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constexpr PinMap map_sgpio_13{4, 8, 5, 12, 4};
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constexpr PinMap map_og_1v8_en{6, 10, 3, 6, 0};
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constexpr PinMap map_r9_1v8_en{5, 0, 2, 9, 0};
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constexpr PinMap map_vregmode{6, 11, 3, 7, 0};
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constexpr PinMap map_og_VAA_en{5, 0, 2, 9, 0};
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constexpr PinMap map_r9_VAA_en{6, 10, 3, 6, 0};
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constexpr PinMap map_rx_mix_bypass{6, 8, 5, 16, 4};
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constexpr PinMap map_tx_mix_bp{5, 2, 2, 11, 0};
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constexpr PinMap map_rx_mix_bp{5, 3, 2, 12, 0};
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constexpr PinMap map_tx_mix_bypass{1, 7, 1, 0, 0};
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constexpr PinMap map_og_rx{2, 5, 5, 5, 4};
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constexpr PinMap map_og_tx{6, 7, 5, 15, 4};
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constexpr PinMap map_r9_rx{2, 7, 0, 7, 0};
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constexpr PinMap map_lpf{5, 1, 2, 10, 0};
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constexpr PinMap map_hpf{4, 0, 2, 0, 0};
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constexpr PinMap map_amp_bypass{2, 10, 0, 14, 0};
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constexpr PinMap map_tx_amp{5, 6, 2, 15, 0};
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constexpr PinMap map_rx_amp{2, 11, 1, 11, 0};
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constexpr PinMap map_tx_amp_pwr{6, 9, 3, 5, 0};
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constexpr PinMap map_rx_amp_pwr{2, 12, 1, 12, 0};
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constexpr PinMap map_ant_bias{4, 4, 2, 4, 0};
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constexpr PinMap map_r9_mcu_clk_en{1, 1, 0, 8, 0};
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constexpr PinMap map_r9_clkout_en{1, 2, 0, 9, 0};
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constexpr PinMap map_r9_clkin_en{6, 7, 5, 15, 4};
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#endif
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constexpr PinMap map_sgpio_0{0, 0, 0, 0, 3};
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constexpr PinMap map_sgpio_1{0, 1, 0, 1, 3};
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constexpr PinMap map_sgpio_2{1, 15, 0, 2, 2};
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constexpr PinMap map_sgpio_3{1, 16, 0, 3, 2};
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constexpr PinMap map_sgpio_5{6, 6, 0, 5, 2};
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constexpr PinMap map_sgpio_6{2, 2, 5, 2, 0};
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constexpr PinMap map_sgpio_7{1, 0, 0, 4, 6};
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constexpr PinMap map_sgpio_11{1, 17, 0, 12, 6};
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constexpr PinMap map_sgpio_12{1, 18, 0, 13, 0};
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constexpr PinMap map_led_usb{4, 1, 2, 1, 0};
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constexpr PinMap map_led_rx{4, 2, 2, 2, 0};
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constexpr PinMap map_led_tx{6, 12, 2, 8, 0};
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constexpr PinMap map_dfu_boot_0{1, 1, 0, 8, 0};
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constexpr PinMap map_dfu_boot_1{1, 2, 0, 9, 0};
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constexpr PinMap map_dfu_button{2, 8, 5, 7, 4};
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constexpr PinMap map_lcd_wrx{2, 9, 1, 10, 0};
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constexpr PinMap map_isp{2, 7, 0, 7, 0};
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#ifdef PRALINE
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// P1 Multiplexer control pins
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constexpr Pin pin_p1_ctrl0{map_p1_ctrl0.scu_port, map_p1_ctrl0.scu_pin}; // SCU: P2_10
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constexpr GPIO p1_ctrl0{pin_p1_ctrl0, map_p1_ctrl0.gpio_port, map_p1_ctrl0.gpio_pad, map_p1_ctrl0.gpio_mode}; // GPIO[0]14
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constexpr Pin pin_p1_ctrl1{map_p1_ctrl1.scu_port, map_p1_ctrl1.scu_pin}; // SCU: P6_8
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constexpr GPIO p1_ctrl1{pin_p1_ctrl1, map_p1_ctrl1.gpio_port, map_p1_ctrl1.gpio_pad, map_p1_ctrl1.gpio_mode}; // GPIO[5]16
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constexpr Pin pin_p1_ctrl2{map_p1_ctrl2.scu_port, map_p1_ctrl2.scu_pin}; // SCU: P6_9
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constexpr GPIO p1_ctrl2{pin_p1_ctrl2, map_p1_ctrl2.gpio_port, map_p1_ctrl2.gpio_pad, map_p1_ctrl2.gpio_mode}; // GPIO[3]5
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// P2 Multiplexer control pins
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constexpr Pin pin_p2_ctrl0{map_p2_ctrl0.scu_port, map_p2_ctrl0.scu_pin}; // SCU: PE_3
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constexpr GPIO p2_ctrl0{pin_p2_ctrl0, map_p2_ctrl0.gpio_port, map_p2_ctrl0.gpio_pad, map_p2_ctrl0.gpio_mode}; // GPIO[7]3
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constexpr Pin pin_p2_ctrl1{map_p2_ctrl1.scu_port, map_p2_ctrl1.scu_pin}; // SCU: PE_4
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constexpr GPIO p2_ctrl1{pin_p2_ctrl1, map_p2_ctrl1.gpio_port, map_p2_ctrl1.gpio_pad, map_p2_ctrl1.gpio_mode}; // GPIO[7]4
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// Trigger pins
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constexpr Pin trigger_out_pin{map_trigger_out.scu_port, map_trigger_out.scu_pin}; // SCU: P2_6
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constexpr GPIO trigger_out{trigger_out_pin, map_trigger_out.gpio_port, map_trigger_out.gpio_pad, map_trigger_out.gpio_mode}; // GPIO[5]6
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constexpr Pin trigger_in_pin{map_trigger_in.scu_port, map_trigger_in.scu_pin}; // SCU: PD_12
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constexpr GPIO trigger_in{trigger_in_pin, map_trigger_in.gpio_port, map_trigger_in.gpio_pad, map_trigger_in.gpio_mode}; // GPIO[6]26
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// Clock input control
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constexpr Pin pin_clkin_ctrl{map_clkin_ctrl.scu_port, map_clkin_ctrl.scu_pin}; // SCU: P1_20
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constexpr GPIO clkin_ctrl{pin_clkin_ctrl, map_clkin_ctrl.gpio_port, map_clkin_ctrl.gpio_pad, map_clkin_ctrl.gpio_mode}; // GPIO[0]15
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// RF507x
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constexpr Pin pin_rf5072_mix_en{map_rf5072_mix_en.scu_port, map_rf5072_mix_en.scu_pin}; // SCU: P9_0
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constexpr GPIO rf5072_mix_en{pin_rf5072_mix_en, map_rf5072_mix_en.gpio_port, map_rf5072_mix_en.gpio_pad, map_rf5072_mix_en.gpio_mode}; // GPIO[4]12
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// Anti-Aliasing filter
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constexpr Pin pin_aa_en{map_aa_en.scu_port, map_aa_en.scu_pin}; // SCU: P1_14
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constexpr GPIO aa_en{pin_aa_en, map_aa_en.gpio_port, map_aa_en.gpio_pad, map_aa_en.gpio_mode}; // GPIO[1]7
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constexpr Pin pin_en_1v2{map_en_1v2.scu_port, map_en_1v2.scu_pin}; // SCU: P8_7
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constexpr GPIO en_1v2{pin_en_1v2, map_en_1v2.gpio_port, map_en_1v2.gpio_pad, map_en_1v2.gpio_mode}; // GPIO[4]7
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constexpr Pin pin_VAA_en{map_VAA_en.scu_port, map_VAA_en.scu_pin}; // SCU: P8_1
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constexpr GPIO VAA_en{pin_VAA_en, map_VAA_en.gpio_port, map_VAA_en.gpio_pad, map_VAA_en.gpio_mode, Polarity::ActiveLow}; // GPIO[4]1
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constexpr Pin pin_led_usb{map_led_usb.scu_port, map_led_usb.scu_pin}; // SCU: P4_1
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constexpr GPIO led_usb{pin_led_usb, map_led_usb.gpio_port, map_led_usb.gpio_pad, map_led_usb.gpio_mode, Polarity::ActiveLow}; // GPIO[2]1
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constexpr Pin pin_led_rx{map_led_rx.scu_port, map_led_rx.scu_pin}; // SCU: P4_2
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constexpr GPIO led_rx{pin_led_rx, map_led_rx.gpio_port, map_led_rx.gpio_pad, map_led_rx.gpio_mode, Polarity::ActiveLow}; // GPIO[2]2
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constexpr Pin pin_led_tx{map_led_tx.scu_port, map_led_tx.scu_pin}; // SCU: P6_12
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constexpr GPIO led_tx{pin_led_tx, map_led_tx.gpio_port, map_led_tx.gpio_pad, map_led_tx.gpio_mode, Polarity::ActiveLow}; // GPIO[2]8
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constexpr Pin pin_led_mcu{map_led_mcu.scu_port, map_led_mcu.scu_pin}; // SCU: P8_6
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constexpr GPIO led_mcu{pin_led_mcu, map_led_mcu.gpio_port, map_led_mcu.gpio_pad, map_led_mcu.gpio_mode, Polarity::ActiveLow}; // GPIO[4]6
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constexpr Pin pin_mix_bypass{map_mix_bypass.scu_port, map_mix_bypass.scu_pin}; // SCU: P6_3
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constexpr GPIO mix_bypass{pin_mix_bypass, map_mix_bypass.gpio_port, map_mix_bypass.gpio_pad, map_mix_bypass.gpio_mode, Polarity::ActiveLow}; // GPIO[3]2
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constexpr Pin pin_tx_enable{map_tx_enable.scu_port, map_tx_enable.scu_pin}; // SCU: P6_5
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constexpr GPIO tx_enable{pin_tx_enable, map_tx_enable.gpio_port, map_tx_enable.gpio_pad, map_tx_enable.gpio_mode}; // GPIO[3]4
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constexpr Pin pin_rf_amp_enable{map_rf_amp_enable.scu_port, map_rf_amp_enable.scu_pin}; // SCU: PA_2
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constexpr GPIO rf_amp_enable{pin_rf_amp_enable, map_rf_amp_enable.gpio_port, map_rf_amp_enable.gpio_pad, map_rf_amp_enable.gpio_mode}; // GPIO[4]9
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constexpr Pin pin_aux_power_enable{map_aux_power_enable.scu_port, map_aux_power_enable.scu_pin}; // SCU: P6_7
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constexpr GPIO aux_power_enable{pin_aux_power_enable, map_aux_power_enable.gpio_port, map_aux_power_enable.gpio_pad, map_aux_power_enable.gpio_mode, Polarity::ActiveLow}; // GPIO[5]15
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constexpr Pin pin_aux_power_oc{map_aux_power_oc.scu_port, map_aux_power_oc.scu_pin}; // SCU: P6_11
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constexpr GPIO aux_power_oc{pin_aux_power_oc, map_aux_power_oc.gpio_port, map_aux_power_oc.gpio_pad, map_aux_power_oc.gpio_mode}; // GPIO[3]7
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constexpr Pin pin_ant_bias_oc{map_ant_bias_oc.scu_port, map_ant_bias_oc.scu_pin}; // SCU: P2_11
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constexpr GPIO ant_bias_oc{pin_ant_bias_oc, map_ant_bias_oc.gpio_port, map_ant_bias_oc.gpio_pad, map_ant_bias_oc.gpio_mode, Polarity::ActiveLow}; // GPIO[1]11
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constexpr Pin pin_pps_in_out{map_pps_in_out.scu_port, map_pps_in_out.scu_pin}; // SCU: P2_5
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constexpr GPIO pps_in_out{pin_pps_in_out, map_pps_in_out.gpio_port, map_pps_in_out.gpio_pad, map_pps_in_out.gpio_mode}; // GPIO[5]5
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#else
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constexpr Pin pin_sgpio_13{map_sgpio_13.scu_port, map_sgpio_13.scu_pin}; // SCU: P4_8
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constexpr GPIO sgpio_13{pin_sgpio_13, map_sgpio_13.gpio_port, map_sgpio_13.gpio_pad, map_sgpio_13.gpio_mode}; // GPIO[5]12
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constexpr Pin pin_og_1v8_en{map_og_1v8_en.scu_port, map_og_1v8_en.scu_pin}; // SCU: P6_10
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constexpr GPIO og_1v8_en{pin_og_1v8_en, map_og_1v8_en.gpio_port, map_og_1v8_en.gpio_pad, map_og_1v8_en.gpio_mode}; // GPIO[3]6
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constexpr Pin pin_r9_1v8_en{map_r9_1v8_en.scu_port, map_r9_1v8_en.scu_pin}; // SCU: P5_0
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constexpr GPIO r9_1v8_en{pin_r9_1v8_en, map_r9_1v8_en.gpio_port, map_r9_1v8_en.gpio_pad, map_r9_1v8_en.gpio_mode}; // GPIO[2]9
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constexpr Pin pin_og_VAA_en{map_og_VAA_en.scu_port, map_og_VAA_en.scu_pin}; // SCU: P5_0
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constexpr GPIO og_VAA_en{pin_og_VAA_en, map_og_VAA_en.gpio_port, map_og_VAA_en.gpio_pad, map_og_VAA_en.gpio_mode, Polarity::ActiveLow}; // GPIO[2]9
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constexpr Pin pin_r9_VAA_en{map_r9_VAA_en.scu_port, map_r9_VAA_en.scu_pin}; // SCU: P6_10
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constexpr GPIO r9_VAA_en{pin_r9_VAA_en, map_r9_VAA_en.gpio_port, map_r9_VAA_en.gpio_pad, map_r9_VAA_en.gpio_mode, Polarity::ActiveLow}; // GPIO[3]6
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constexpr Pin pin_led_usb{map_led_usb.scu_port, map_led_usb.scu_pin}; // SCU: P4_1
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constexpr GPIO led_usb{pin_led_usb, map_led_usb.gpio_port, map_led_usb.gpio_pad, map_led_usb.gpio_mode}; // GPIO[2]1
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constexpr Pin pin_led_rx{map_led_rx.scu_port, map_led_rx.scu_pin}; // SCU: P4_2
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constexpr GPIO led_rx{pin_led_rx, map_led_rx.gpio_port, map_led_rx.gpio_pad, map_led_rx.gpio_mode}; // GPIO[2]2
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constexpr Pin pin_led_tx{map_led_tx.scu_port, map_led_tx.scu_pin}; // SCU: P6_12
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constexpr GPIO led_tx{pin_led_tx, map_led_tx.gpio_port, map_led_tx.gpio_pad, map_led_tx.gpio_mode}; // GPIO[2]8
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constexpr Pin pin_rx_mix_bypass{map_rx_mix_bypass.scu_port, map_rx_mix_bypass.scu_pin}; // SCU: P6_8
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constexpr GPIO rx_mix_bypass{pin_rx_mix_bypass, map_rx_mix_bypass.gpio_port, map_rx_mix_bypass.gpio_pad, map_rx_mix_bypass.gpio_mode}; // GPIO[5]16
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constexpr Pin pin_tx_mix_bp{map_tx_mix_bp.scu_port, map_tx_mix_bp.scu_pin}; // SCU: P5_2
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constexpr GPIO tx_mix_bp{pin_tx_mix_bp, map_tx_mix_bp.gpio_port, map_tx_mix_bp.gpio_pad, map_tx_mix_bp.gpio_mode}; // GPIO[2]11
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constexpr Pin pin_rx_mix_bp{map_rx_mix_bp.scu_port, map_rx_mix_bp.scu_pin}; // SCU: P5_3
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constexpr GPIO rx_mix_bp{pin_rx_mix_bp, map_rx_mix_bp.gpio_port, map_rx_mix_bp.gpio_pad, map_rx_mix_bp.gpio_mode}; // GPIO[2]12
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constexpr Pin pin_tx_mix_bypass{map_tx_mix_bypass.scu_port, map_tx_mix_bypass.scu_pin}; // SCU: P1_7
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constexpr GPIO tx_mix_bypass{pin_tx_mix_bypass, map_tx_mix_bypass.gpio_port, map_tx_mix_bypass.gpio_pad, map_tx_mix_bypass.gpio_mode, Polarity::ActiveLow}; // GPIO[1]0
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constexpr Pin pin_og_rx{map_og_rx.scu_port, map_og_rx.scu_pin}; // SCU: P2_5
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constexpr GPIO og_rx{pin_og_rx, map_og_rx.gpio_port, map_og_rx.gpio_pad, map_og_rx.gpio_mode}; // GPIO[5]5
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constexpr Pin pin_og_tx{map_og_tx.scu_port, map_og_tx.scu_pin}; // SCU: P6_7
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constexpr GPIO og_tx{pin_og_tx, map_og_tx.gpio_port, map_og_tx.gpio_pad, map_og_tx.gpio_mode}; // GPIO[5]15
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constexpr Pin pin_r9_rx{map_r9_rx.scu_port, map_r9_rx.scu_pin}; // SCU: P2_7
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constexpr GPIO r9_rx{pin_r9_rx, map_r9_rx.gpio_port, map_r9_rx.gpio_pad, map_r9_rx.gpio_mode}; // GPIO[0]7
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constexpr Pin pin_hpf{map_hpf.scu_port, map_hpf.scu_pin}; // SCU: P4_0
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constexpr GPIO hpf{pin_hpf, map_hpf.gpio_port, map_hpf.gpio_pad, map_hpf.gpio_mode}; // GPIO[2]0
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constexpr Pin pin_amp_bypass{map_amp_bypass.scu_port, map_amp_bypass.scu_pin}; // SCU: P2_10
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constexpr GPIO amp_bypass{pin_amp_bypass, map_amp_bypass.gpio_port, map_amp_bypass.gpio_pad, map_amp_bypass.gpio_mode}; // GPIO[0]14
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constexpr Pin pin_tx_amp{map_tx_amp.scu_port, map_tx_amp.scu_pin}; // SCU: P5_6
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constexpr GPIO tx_amp{pin_tx_amp, map_tx_amp.gpio_port, map_tx_amp.gpio_pad, map_tx_amp.gpio_mode}; // GPIO[2]15
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constexpr Pin pin_rx_amp{map_rx_amp.scu_port, map_rx_amp.scu_pin}; // SCU: P2_11
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constexpr GPIO rx_amp{pin_rx_amp, map_rx_amp.gpio_port, map_rx_amp.gpio_pad, map_rx_amp.gpio_mode}; // GPIO[1]11
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constexpr Pin pin_tx_amp_pwr{map_tx_amp_pwr.scu_port, map_tx_amp_pwr.scu_pin}; // SCU: P6_9
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constexpr GPIO tx_amp_pwr{pin_tx_amp_pwr, map_tx_amp_pwr.gpio_port, map_tx_amp_pwr.gpio_pad, map_tx_amp_pwr.gpio_mode, Polarity::ActiveLow}; // GPIO[3]5
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constexpr Pin pin_rx_amp_pwr{map_rx_amp_pwr.scu_port, map_rx_amp_pwr.scu_pin}; // SCU: P2_12
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constexpr GPIO rx_amp_pwr{pin_rx_amp_pwr, map_rx_amp_pwr.gpio_port, map_rx_amp_pwr.gpio_pad, map_rx_amp_pwr.gpio_mode, Polarity::ActiveLow}; // GPIO[1]12
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constexpr Pin pin_r9_mcu_clk_en{map_r9_mcu_clk_en.scu_port, map_r9_mcu_clk_en.scu_pin}; // SCU: P1_1
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constexpr GPIO r9_mcu_clk_en{pin_r9_mcu_clk_en, map_r9_mcu_clk_en.gpio_port, map_r9_mcu_clk_en.gpio_pad, map_r9_mcu_clk_en.gpio_mode}; // GPIO[0]8
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constexpr Pin pin_r9_clkout_en{map_r9_clkout_en.scu_port, map_r9_clkout_en.scu_pin}; // SCU: P1_2
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constexpr GPIO r9_clkout_en{pin_r9_clkout_en, map_r9_clkout_en.gpio_port, map_r9_clkout_en.gpio_pad, map_r9_clkout_en.gpio_mode}; // GPIO[0]9
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constexpr Pin pin_r9_clkin_en{map_r9_clkin_en.scu_port, map_r9_clkin_en.scu_pin}; // SCU: P6_7
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constexpr GPIO r9_clkin_en{pin_r9_clkin_en, map_r9_clkin_en.gpio_port, map_r9_clkin_en.gpio_pad, map_r9_clkin_en.gpio_mode}; // GPIO[5]15
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static const motocon_pwm_resources_t motocon_pwm_resources = {
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.base = {.clk = &LPC_CGU->BASE_APB1_CLK, .stat = &LPC_CCU1->BASE_STAT, .stat_mask = (1 << 1)},
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.branch = {.cfg = &LPC_CCU1->CLK_APB1_MOTOCON_PWM_CFG, .stat = &LPC_CCU1->CLK_APB1_MOTOCON_PWM_STAT},
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.reset = {.output_index = 38},
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};
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static const scu_setup_t pin_setup_vaa_enablex_pwm = {5, 0, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}};
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static const scu_setup_t pin_setup_vaa_enablex_gpio_og = {map_og_VAA_en.scu_port, map_og_VAA_en.scu_pin, scu_config_normal_drive_t{.mode = map_og_VAA_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}};
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static const scu_setup_t pin_setup_vaa_enablex_gpio_r9 = {map_r9_VAA_en.scu_port, map_r9_VAA_en.scu_pin, scu_config_normal_drive_t{.mode = map_r9_VAA_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}};
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#endif
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// SGPIO
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constexpr Pin pin_sgpio_0{map_sgpio_0.scu_port, map_sgpio_0.scu_pin}; // SCU: P0_0
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constexpr GPIO sgpio_0{pin_sgpio_0, map_sgpio_0.gpio_port, map_sgpio_0.gpio_pad, map_sgpio_0.gpio_mode}; // GPIO[0]0
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constexpr Pin pin_sgpio_1{map_sgpio_1.scu_port, map_sgpio_1.scu_pin}; // SCU: P0_1
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constexpr GPIO sgpio_1{pin_sgpio_1, map_sgpio_1.gpio_port, map_sgpio_1.gpio_pad, map_sgpio_1.gpio_mode}; // GPIO[0]1
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constexpr Pin pin_sgpio_2{map_sgpio_2.scu_port, map_sgpio_2.scu_pin}; // SCU: P1_15
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constexpr GPIO sgpio_2{pin_sgpio_2, map_sgpio_2.gpio_port, map_sgpio_2.gpio_pad, map_sgpio_2.gpio_mode}; // GPIO[0]2
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constexpr Pin pin_sgpio_3{map_sgpio_3.scu_port, map_sgpio_3.scu_pin}; // SCU: P1_16
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constexpr GPIO sgpio_3{pin_sgpio_3, map_sgpio_3.gpio_port, map_sgpio_3.gpio_pad, map_sgpio_3.gpio_mode}; // GPIO[0]3
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constexpr Pin pin_sgpio_4{map_sgpio_4.scu_port, map_sgpio_4.scu_pin}; // SCU: P6_3, PRALINE: P9_4
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constexpr GPIO sgpio_4{pin_sgpio_4, map_sgpio_4.gpio_port, map_sgpio_4.gpio_pad, map_sgpio_4.gpio_mode}; // GPIO[6]3 PRALINE: GPIO[5]17
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constexpr Pin pin_sgpio_5{map_sgpio_5.scu_port, map_sgpio_5.scu_pin}; // SCU: P6_6
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constexpr GPIO sgpio_5{pin_sgpio_5, map_sgpio_5.gpio_port, map_sgpio_5.gpio_pad, map_sgpio_5.gpio_mode}; // GPIO[0]5
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constexpr Pin pin_sgpio_6{map_sgpio_6.scu_port, map_sgpio_6.scu_pin}; // SCU: P2_2
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constexpr GPIO sgpio_6{pin_sgpio_6, map_sgpio_6.gpio_port, map_sgpio_6.gpio_pad, map_sgpio_6.gpio_mode}; // GPIO[5]2
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constexpr Pin pin_sgpio_7{map_sgpio_7.scu_port, map_sgpio_7.scu_pin}; // SCU: P1_0
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constexpr GPIO sgpio_7{pin_sgpio_7, map_sgpio_7.gpio_port, map_sgpio_7.gpio_pad, map_sgpio_7.gpio_mode}; // GPIO[0]4
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constexpr Pin pin_sgpio_8{map_sgpio_8.scu_port, map_sgpio_8.scu_pin}; // SCU: P9_6, PRALINE: P8_0
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constexpr GPIO sgpio_8{pin_sgpio_8, map_sgpio_8.gpio_port, map_sgpio_8.gpio_pad, map_sgpio_8.gpio_mode}; // GPIO[4]11, PRALINE: GPIO[4]0
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constexpr Pin pin_sgpio_9{map_sgpio_9.scu_port, map_sgpio_9.scu_pin}; // SCU: P4_3, PRALINE: P9_3
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constexpr GPIO sgpio_9{pin_sgpio_9, map_sgpio_9.gpio_port, map_sgpio_9.gpio_pad, map_sgpio_9.gpio_mode}; // GPIO[2]3, PRALINE: GPIO[4]12
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constexpr Pin pin_sgpio_10{map_sgpio_10.scu_port, map_sgpio_10.scu_pin}; // SCU: P1_14, PRALINE: P8_2
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constexpr GPIO sgpio_10{pin_sgpio_10, map_sgpio_10.gpio_port, map_sgpio_10.gpio_pad, map_sgpio_10.gpio_mode}; // GPIO[1]7, PRALINE: GPIO[4]2
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constexpr Pin pin_sgpio_11{map_sgpio_11.scu_port, map_sgpio_11.scu_pin}; // SCU: P1_17
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constexpr GPIO sgpio_11{pin_sgpio_11, map_sgpio_11.gpio_port, map_sgpio_11.gpio_pad, map_sgpio_11.gpio_mode}; // GPIO[0]17
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constexpr Pin pin_sgpio_12{map_sgpio_12.scu_port, map_sgpio_12.scu_pin}; // SCU: P1_18
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constexpr GPIO sgpio_12{pin_sgpio_12, map_sgpio_12.gpio_port, map_sgpio_12.gpio_pad, map_sgpio_12.gpio_mode}; // GPIO[0]13
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constexpr Pin pin_vregmode{map_vregmode.scu_port, map_vregmode.scu_pin}; // SCU: P6_11, PRALINE: P4_9
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constexpr GPIO vregmode{pin_vregmode, map_vregmode.gpio_port, map_vregmode.gpio_pad, map_vregmode.gpio_mode}; // GPIO[3]7, PRALINE: GPIO[5]13
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constexpr Pin pin_lpf{map_lpf.scu_port, map_lpf.scu_pin}; // SCU: P5_1, PRALINE: PA_1
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constexpr GPIO lpf{pin_lpf, map_lpf.gpio_port, map_lpf.gpio_pad, map_lpf.gpio_mode}; // GPIO[2]10, PRALINE: GPIO[4]8
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constexpr Pin pin_ant_bias{map_ant_bias.scu_port, map_ant_bias.scu_pin}; // SCU: R9: P4_4 , PRALINE: P2_12
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constexpr GPIO ant_bias{pin_ant_bias, map_ant_bias.gpio_port, map_ant_bias.gpio_pad, map_ant_bias.gpio_mode, Polarity::ActiveLow}; // R9: GPIO[2]4, PRALINE: GPIO[1]12
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constexpr Pin pin_dfu_boot_0{map_dfu_boot_0.scu_port, map_dfu_boot_0.scu_pin}; // SCU: P1_1
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constexpr GPIO dfu_boot_0{pin_dfu_boot_0, map_dfu_boot_0.gpio_port, map_dfu_boot_0.gpio_pad, map_dfu_boot_0.gpio_mode}; // GPIO[0]8
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constexpr Pin pin_dfu_boot_1{map_dfu_boot_1.scu_port, map_dfu_boot_1.scu_pin}; // SCU: P1_2
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constexpr GPIO dfu_boot_1{pin_dfu_boot_1, map_dfu_boot_1.gpio_port, map_dfu_boot_1.gpio_pad, map_dfu_boot_1.gpio_mode}; // GPIO[0]9
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constexpr Pin pin_dfu_button{map_dfu_button.scu_port, map_dfu_button.scu_pin}; // SCU: P2_8
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constexpr GPIO dfu_button{pin_dfu_button, map_dfu_button.gpio_port, map_dfu_button.gpio_pad, map_dfu_button.gpio_mode}; // GPIO[5]7
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constexpr Pin pin_lcd_wrx{map_lcd_wrx.scu_port, map_lcd_wrx.scu_pin}; // SCU: P2_9
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constexpr GPIO lcd_wrx{pin_lcd_wrx, map_lcd_wrx.gpio_port, map_lcd_wrx.gpio_pad, map_lcd_wrx.gpio_mode}; // GPIO[1]10
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constexpr Pin pin_isp{map_isp.scu_port, map_isp.scu_pin}; // SCU: P2_7
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constexpr GPIO dfu_isp{pin_isp, map_isp.gpio_port, map_isp.gpio_pad, map_isp.gpio_mode}; // GPIO[0]7
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} // namespace gpio_control
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namespace power_control {
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void vaa_power_on(void);
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void vaa_power_off(void);
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#ifdef PRALINE
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void aux_power_on(void);
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void aux_power_off(void);
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#endif
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void core_power_on(void);
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void core_power_off(void);
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} // namespace power_control
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#endif /*__GPIO_H__*/
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