mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-08-18 05:34:01 +00:00
gullradriel
8f5b25b10d
* fix clock init and add mayhem tx capacity * aligned external clock and RX config * fix(clock): cap TX interpolation to x16 to prevent doubled waveform speed The TX gateware only implements interpolation factors x1..x16 (tx_intrp 0..4), but the rate search could select n==5 (x32) for very low TX sample rates. That left the AFE/CLK0/CLK1 running at the x32 rate while the FPGA only interpolated by x16, clocking the TX datapath at twice the gateware output rate. Cap afe_rate and _resampling_n to the x16 limit in TX so the clocks stay aligned with the interpolation setting. * fix(praline): source PLL1 from 40MHz GP_CLKIN instead of 12MHz XTAL For the intermediate 90-110MHz PLL1 stepping stage, source PLL1 from GP_CLKIN (Si5351 CLK2/MCU_CLK at 40MHz) giving N=2, M=10, Fclk=100MHz, rather than the on-chip 12MHz XTAL bootstrap path. This matches the non-PRALINE path. Remove the dead commented-out XTAL enable/PLL code. * docs(fpga_bridge): correct register 0x03 description for PRALINE gateware Register 0x03 is RX_DIGITAL_GAIN in RX and TX_NCO_CTRL in TX, not RX_PSTEP. * Fix fpga_tx_set_nco_enable to use FPGA_REG3_TX_NCO_CTRL (0x03)
98 lines
2.8 KiB
C++
98 lines
2.8 KiB
C++
/*
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* Copyright (C) 2015 Jared Boone, ShareBrained Technology, Inc.
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* Copyright (C) 2016 Furrtek
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* Copyright (C) 2023 Kyle Reed
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __TRANSMITTER_MODEL_H__
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#define __TRANSMITTER_MODEL_H__
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#include <cstdint>
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#include <cstddef>
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#include "app_settings.hpp"
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#include "hackrf_hal.hpp"
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#include "max2837.hpp"
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#include "message.hpp"
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#include "receiver_model.hpp"
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#include "rf_path.hpp"
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#include "signal.hpp"
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class TransmitterModel {
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public:
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struct settings_t {
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uint32_t baseband_bandwidth = max283x::filter::bandwidth_minimum;
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uint32_t sampling_rate = 3'072'000;
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uint32_t channel_bandwidth = 1;
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/* Platform default chosen to avoid PRALINE MAX2831 overdrive while
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* preserving legacy HackRF One behavior. */
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uint8_t tx_gain_db = hackrf::one::default_tx_gain_db;
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bool rf_amp = false;
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};
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/* The frequency to transmit on. */
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rf::Frequency target_frequency() const;
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void set_target_frequency(rf::Frequency f);
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uint32_t baseband_bandwidth() const;
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void set_baseband_bandwidth(uint32_t v);
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// TODO: Doesn't actually affect radio.
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uint32_t channel_bandwidth() const;
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void set_channel_bandwidth(uint32_t v);
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uint32_t sampling_rate() const;
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void set_sampling_rate(uint32_t v);
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uint8_t tx_gain() const;
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void set_tx_gain(uint8_t v_db);
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bool rf_amp() const;
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void set_rf_amp(bool enabled);
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void set_antenna_bias();
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void enable();
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void disable();
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void initialize();
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void configure_from_app_settings(const app_settings::AppSettings& settings);
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/* Get access to the underlying settings to allow
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* values to be set directly without calling update. */
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settings_t& settings() { return settings_; }
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private:
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settings_t settings_{};
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bool enabled_ = false;
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SignalToken signal_token_tick_second{};
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void update_tuning_frequency();
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void update_baseband_bandwidth();
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void update_sampling_rate();
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void update_tx_gain();
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void update_rf_amp();
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void update_antenna_bias();
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void on_tick_second();
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};
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#endif /*__TRANSMITTER_MODEL_H__*/
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