mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-09-11 17:19:29 +00:00
qwer123
178 lines
5.3 KiB
C
178 lines
5.3 KiB
C
/*
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* FPGA Bridge Header - PRALINE iCE40 FPGA interface
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*
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* Provides functions for initializing and accessing the FPGA on HackRF Pro (PRALINE).
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*/
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#ifndef __FPGA_BRIDGE_H__
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#define __FPGA_BRIDGE_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef PRALINE
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/*
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* RX path.
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*
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* NOTE: the register map below is the one the loaded bitstream actually
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* implements. Ground truth is hackrf/firmware/fpga/top/standard.py plus
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* hackrf/firmware/common/fpga_regs.def; Mayhem, hackrf_usb and debug_for_adsb
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* all load a byte-identical praline_fpga.bin, so that map applies here too.
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*
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* An earlier "legacy PRALINE software map" claimed register 0x03 was an RX
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* digital gain and 0x04/0x05 were DC-block width / adaptation rate. The
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* gateware has none of those: 0x03 is rx_pstep (whose top two bits are the
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* quarter-rate shift) and 0x04/0x05 are TX registers. Writing the old "RX DC
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* width" value of 0x01 to 0x04 actually set tx_ctrl[0] and switched the TX NCO
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* on, and every write of the fictional digital gain to 0x03 cleared the
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* quarter shift.
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*/
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#define FPGA_REG_RX_PSTEP 0x03 /* RX phase step; bits [7:6] = quarter shift */
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/*
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* TX path must match the currently built PRALINE standard gateware in
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* hackrf/firmware/fpga/top/standard.py:
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* 0x04 tx_ctrl
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* 0x05 tx_intrp
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* 0x06 tx_pstep
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*/
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#define FPGA_REG_TX_CONTROL 0x04
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#define FPGA_REG_TX_INTERP 0x05
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#define FPGA_REG_TX_PHASE_STEP 0x06
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/*
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* FPGA Operating Mode
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*/
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typedef enum {
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FPGA_MODE_OFF = 0,
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FPGA_MODE_RX,
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FPGA_MODE_TX
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} fpga_mode_t;
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/*
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* FPGA Register Addresses
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*
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* From hackrf/firmware/fpga/top/standard.py (spi_regs.add_register):
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* 0x01 ctrl 8 bits
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* 0x02 rx_decim 3 bits
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* 0x03 rx_pstep 8 bits
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* 0x04 tx_ctrl 1 bit
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* 0x05 tx_intrp 3 bits
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* 0x06 tx_pstep 8 bits
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*
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* There is no RX gain register: rx_decim selects half-band FIR stages
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* (hbfir1..hbfir5), which are unity-gain, so there is no CIC bit growth to
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* renormalise.
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*/
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#define FPGA_REG_CTRL 0x01 /* Control register */
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#define FPGA_REG_DECIM 0x02 /* RX decimation (log2, bits [2:0]) */
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/* 0x03..0x06 are FPGA_REG_RX_PSTEP / FPGA_REG_TX_CONTROL /
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* FPGA_REG_TX_INTERP / FPGA_REG_TX_PHASE_STEP, defined above. */
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/*
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* Register 1 (CTRL) Bit Definitions
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* standard.py: ctrl[0] -> dc_block.enable, ctrl[6] -> prbs, ctrl[7] -> trigger_en.
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* Nothing else in this register is decoded.
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*/
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#define FPGA_CTRL_DC_BLOCK_EN (1 << 0) /* DC block enable */
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#define FPGA_CTRL_PRBS_EN (1 << 6) /* PRBS test mode */
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#define FPGA_CTRL_TRIGGER_EN (1 << 7) /* External trigger enable */
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/*
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* Register 3 (RX_PSTEP) Bit Definitions
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* standard.py: rx_pstep[6] -> quarter_shift.enable, rx_pstep[7] -> quarter_shift.up.
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* Same encoding as fpga_quarter_shift_mode_t << 6 in hackrf/firmware/common/fpga.c.
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*/
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/* Position of that 2-bit field inside rx_pstep, for direct register writes. */
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#define FPGA_RX_QUARTER_SHIFT_SHIFT 6
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#define FPGA_RX_QUARTER_SHIFT_MASK 0xC0
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/* Mode values, matching fpga_quarter_shift_mode_t in
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* hackrf/firmware/common/fpga.h. Pass these to
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* fpga_rx_set_quarter_shift_mode(), which shifts them into place. */
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#define FPGA_QUARTER_SHIFT_MODE_NONE 0b00
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#define FPGA_QUARTER_SHIFT_MODE_UP 0b11
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#define FPGA_QUARTER_SHIFT_MODE_DOWN 0b01
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/*
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* Register 4 (TX_CTRL) / 5 (TX_INTRP) / 6 (TX_PSTEP) Bit Definitions
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*/
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#define FPGA_TX_NCO_EN (1 << 0) /* tx_ctrl[0]: NCO enable */
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#define FPGA_TX_INTERP_MASK 0x07 /* tx_intrp bits [2:0] */
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#define FPGA_TX_PHASE_STEP_MASK 0xFF /* tx_pstep bits [7:0] */
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/*
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* Core Functions
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*/
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/* Initialize the FPGA - loads bitstream from SPIFI flash
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* Returns: 0 on success, non-zero on failure */
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int fpga_bridge_init(uint8_t* mem_base);
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/* Set operating mode - MUST be called before using mode-specific functions
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* This ensures registers 3-5 are interpreted correctly */
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void fpga_set_mode(fpga_mode_t mode);
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/* Get current operating mode */
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fpga_mode_t fpga_get_mode(void);
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/*
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* Low-Level Register Access (use with caution)
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*/
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uint8_t fpga_register_read(uint8_t reg);
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void fpga_register_write(uint8_t reg, uint8_t value);
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/*
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* RX Mode Functions (only valid when mode == FPGA_MODE_RX)
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*/
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void fpga_rx_set_decimation(uint8_t ratio);
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/* mode is the gateware encoding: 0b00 none, 0b11 up, 0b01 down. */
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void fpga_rx_set_quarter_shift_mode(uint8_t mode);
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void fpga_rx_enable_dc_block(bool enable);
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/*
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* TX Mode Functions (only valid when mode == FPGA_MODE_TX)
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*/
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void fpga_tx_set_interpolation(uint8_t ratio);
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void fpga_tx_set_nco_enable(bool enable);
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void fpga_tx_set_phase_step(uint8_t step);
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/*
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* Debug Functions
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*/
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/*
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* Read an FPGA register via SPI
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* reg: Register number (1-5)
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* Returns: Register value, or 0xFF if invalid register
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*
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* FPGA Register Map (hackrf/firmware/fpga/top/standard.py):
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* Reg 1 (CTRL): DC_BLOCK(b0), PRBS(b6), TRIGGER_EN(b7)
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* Reg 2 (RX_DECIM): Decimation ratio, log2 [2:0]
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* Reg 3 (RX_PSTEP): QUARTER_SHIFT_EN(b6), QUARTER_SHIFT_UP(b7)
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* Reg 4 (TX_CTRL): NCO_EN(b0)
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* Reg 5 (TX_INTRP): Interpolation ratio, log2 [2:0]
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* Reg 6 (TX_PSTEP): NCO phase step [7:0]
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*/
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uint8_t fpga_debug_register_read(uint8_t reg);
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/*
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* Write an FPGA register via SPI
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* reg: Register number (1-5)
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* value: Value to write
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*/
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void fpga_debug_register_write(uint8_t reg, uint8_t value);
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#endif /* PRALINE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __FPGA_BRIDGE_H__ */
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