mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-09-11 09:09:29 +00:00
stafur
9a3c2cc6ac
* Cleaned up #ifndef PRALINE and updated logic to being with #ifdef PRALINE entries where possible to make logic flow for PRALINE code execution pipeline clearer. Cleaned up compiletime warnings for PRALINE related codebase updates. * Addressed comments provided by copilot during PR review. Combed through frequency definitions for consistency between PLL A and PLL B register definitions for CLKs 0-7. Ensured CLK3/LK6 <- SMA PORTs and CLK7 <- not utiliized are disabled during core development phase to support root cause analysis of any spectral artifacts. Updated MCU frequency to 40MHz to ensure audio harmonics are outside FM radio band range (< 80 MHz, >120MHz) and added comments clarifying choice of 40 over 10 MHz for potential future root cause analysis in other bands where audio may be expected as needed. Added CLK6 and CLK7 to Clocks Status View Debug display. Moved CLK defintions and PLL instantiations for components that are most RF sensitive to PLL A. Left others in PLL B. That is move FPGA CLK1 to PLL B, while moving CLK2, CLK4, and CLK5 to PLL A. * Cleaned up PLL A and B XTAL reference checks relative to 800 MHz. * Encapsulated HackRF Pro Praline debug and status vies into a single Pro Debug submenu as part of clean up. * Fixed BLE RX Out of Memory error. Updated LPC43xx ld scripts to accouint for additional HackRF Pro praline memory. * Addressed copilot comments for ble_rx_app by adding recent_entries_view.set_dirty. Updated ble_rx_app for easier use with heap limit set to one less than recent entries max limit. * Addressed copilot comments by updating comment clarity in source files. Updated ui_debug to allow for return reference if set for PRO debug menu item. * Improved readability of intialization parameters for the FPGA registers, and addressed 20Mhz nulls by initializing DC Notch width with standard setting, and DC Adaptiation rate with a balanced setting. * Ran format-code.sh * Added option to allow for user to set number if entries in recent list. Default is set to a relatively stable 32. * Removed #ifdef PRALINE pragmas from ble_rx_app such that HackRF One can also use the updated UI widget to allow for user to set number of entries in recent list. * Ran format-code.sh
168 lines
4.9 KiB
C
168 lines
4.9 KiB
C
/*
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* FPGA Bridge Header - PRALINE iCE40 FPGA interface
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*
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* Provides functions for initializing and accessing the FPGA on HackRF Pro (PRALINE).
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*/
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#ifndef __FPGA_BRIDGE_H__
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#define __FPGA_BRIDGE_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef PRALINE
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/* FPGA Register Map Address 0x03 (Dual Purpose) */
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#define FPGA_REG_RX_DIGITAL_GAIN 0x03 /* Digital Shift / scaling (RX Mode) */
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#define FPGA_REG_TX_CONTROL 0x03 /* NCO_EN and TX flags (TX Mode) */
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/* FPGA Register Map Address 0x04 (Shared) */
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#define FPGA_REG_RX_DC_BLOCK_WIDTH 0x04 /* Notch filter cutoff (RX Mode) */
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#define FPGA_REG_TX_INTERP 0x04 /* Interpolation ratio (TX Mode) */
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/* FPGA Register Map Address 0x05 (Shared) */
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#define FPGA_REG_RX_DC_ADAPT_RATE 0x05 /* Settle time/Integration (RX Mode) */
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#define FPGA_REG_TX_PHASE_STEP 0x05 /* NCO frequency step (TX Mode) */
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/*
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* FPGA Operating Mode
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*/
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typedef enum {
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FPGA_MODE_OFF = 0,
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FPGA_MODE_RX,
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FPGA_MODE_TX
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} fpga_mode_t;
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/*
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* FPGA Register Addresses
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* Note: Registers 3-5 are dual-purpose (meaning depends on RX/TX mode)
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*/
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#define FPGA_REG_CTRL 0x01 /* Control register */
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#define FPGA_REG_DECIM 0x02 /* Decimation (RX) / unused (TX) */
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#define FPGA_REG_SHARED_3 0x03 /* Dual-purpose register */
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#define FPGA_REG_SHARED_4 0x04 /* Dual-purpose register */
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#define FPGA_REG_SHARED_5 0x05 /* Dual-purpose register */
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/*
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* Register 1 (CTRL) Bit Definitions
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*/
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#define FPGA_CTRL_DC_BLOCK_EN (1 << 0) /* DC block enable */
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#define FPGA_CTRL_QUARTER_SHIFT_EN (1 << 1) /* Quarter-rate shift enable */
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#define FPGA_CTRL_QUARTER_SHIFT_UP (1 << 2) /* Shift direction: 1=up, 0=down */
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#define FPGA_CTRL_TX_MODE (1 << 5) /* TX mode indicator (if applicable) */
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#define FPGA_CTRL_PRBS_EN (1 << 6) /* PRBS test mode */
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#define FPGA_CTRL_TRIGGER_EN (1 << 7) /* External trigger enable */
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/*
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* Register 3 Dual-Purpose Definitions
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*/
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/* RX Mode: Digital gain/shift */
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#define FPGA_REG3_RX_DIGITAL_GAIN 0x03
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#define FPGA_RX_GAIN_SHIFT_MASK 0x0F /* Bits [3:0] - shift amount */
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/* TX Mode: NCO control */
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#define FPGA_REG3_TX_NCO_CTRL 0x03
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#define FPGA_TX_NCO_EN (1 << 0) /* NCO enable */
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#define FPGA_TX_NCO_INVERT (1 << 1) /* Invert spectrum */
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/*
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* Register 4 Dual-Purpose Definitions
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*/
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/* RX Mode: DC block notch width */
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#define FPGA_REG4_RX_DC_WIDTH 0x04
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#define FPGA_RX_DC_WIDTH_MASK 0x07 /* Bits [2:0] */
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/* TX Mode: Interpolation ratio */
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#define FPGA_REG4_TX_INTERP 0x04
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#define FPGA_TX_INTERP_MASK 0x07 /* Bits [2:0] */
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/*
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* Register 5 Dual-Purpose Definitions
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*/
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/* RX Mode: DC block adaptation rate */
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#define FPGA_REG5_RX_DC_RATE 0x05
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#define FPGA_RX_DC_RATE_MASK 0xFF /* Bits [7:0] */
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/* TX Mode: NCO phase step (frequency) */
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#define FPGA_REG5_TX_PHASE_STEP 0x05
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#define FPGA_TX_PHASE_STEP_MASK 0xFF /* Bits [7:0] */
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/* Export default values so other methods can use them */
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#define FPGA_RX_DEFAULT_DIGITAL_GAIN 0x00
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#define FPGA_RX_DEFAULT_DC_WIDTH 0x04
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#define FPGA_RX_DEFAULT_ADAPT_RATE 0x08
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/*
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* Core Functions
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*/
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/* Initialize the FPGA - loads bitstream from SPIFI flash
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* Returns: 0 on success, non-zero on failure */
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int fpga_bridge_init(void);
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/* Set operating mode - MUST be called before using mode-specific functions
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* This ensures registers 3-5 are interpreted correctly */
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void fpga_set_mode(fpga_mode_t mode);
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/* Get current operating mode */
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fpga_mode_t fpga_get_mode(void);
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/*
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* Low-Level Register Access (use with caution)
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*/
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uint8_t fpga_register_read(uint8_t reg);
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void fpga_register_write(uint8_t reg, uint8_t value);
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/*
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* RX Mode Functions (only valid when mode == FPGA_MODE_RX)
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*/
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void fpga_rx_set_decimation(uint8_t ratio);
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void fpga_rx_set_digital_gain(uint8_t shift);
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void fpga_rx_set_dc_block_width(uint8_t width);
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void fpga_rx_set_dc_adapt_rate(uint8_t rate);
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void fpga_rx_enable_dc_block(bool enable);
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/*
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* TX Mode Functions (only valid when mode == FPGA_MODE_TX)
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*/
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void fpga_tx_set_interpolation(uint8_t ratio);
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void fpga_tx_set_nco_enable(bool enable);
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void fpga_tx_set_phase_step(uint8_t step);
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/*
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* Debug Functions
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*/
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/*
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* Read an FPGA register via SPI
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* reg: Register number (1-5)
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* Returns: Register value, or 0xFF if invalid register
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*
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* FPGA Register Map:
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* Reg 1 (CTRL): DC_BLOCK(b0), QUARTER_SHIFT_EN(b1), QUARTER_SHIFT_UP(b2), PRBS(b6), TRIGGER_EN(b7)
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* Reg 2 (RX_DECIM): Decimation ratio [2:0]
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* Reg 3 (RX/TX): RX Digital Shift OR TX NCO Control
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* Reg 4 (RX_DC_BLOCK_WIDTH/TX_INTERP) [2:0]
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* Reg 5 (RX_DC_ADAPT_RATE/TX_PSTEP) [7:0]
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*/
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uint8_t fpga_debug_register_read(uint8_t reg);
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/*
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* Write an FPGA register via SPI
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* reg: Register number (1-5)
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* value: Value to write
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*/
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void fpga_debug_register_write(uint8_t reg, uint8_t value);
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#endif /* PRALINE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __FPGA_BRIDGE_H__ */
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