mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-08-16 21:03:24 +00:00
gullradriel
8f5b25b10d
* fix clock init and add mayhem tx capacity * aligned external clock and RX config * fix(clock): cap TX interpolation to x16 to prevent doubled waveform speed The TX gateware only implements interpolation factors x1..x16 (tx_intrp 0..4), but the rate search could select n==5 (x32) for very low TX sample rates. That left the AFE/CLK0/CLK1 running at the x32 rate while the FPGA only interpolated by x16, clocking the TX datapath at twice the gateware output rate. Cap afe_rate and _resampling_n to the x16 limit in TX so the clocks stay aligned with the interpolation setting. * fix(praline): source PLL1 from 40MHz GP_CLKIN instead of 12MHz XTAL For the intermediate 90-110MHz PLL1 stepping stage, source PLL1 from GP_CLKIN (Si5351 CLK2/MCU_CLK at 40MHz) giving N=2, M=10, Fclk=100MHz, rather than the on-chip 12MHz XTAL bootstrap path. This matches the non-PRALINE path. Remove the dead commented-out XTAL enable/PLL code. * docs(fpga_bridge): correct register 0x03 description for PRALINE gateware Register 0x03 is RX_DIGITAL_GAIN in RX and TX_NCO_CTRL in TX, not RX_PSTEP. * Fix fpga_tx_set_nco_enable to use FPGA_REG3_TX_NCO_CTRL (0x03)
100 lines
3.0 KiB
C++
100 lines
3.0 KiB
C++
/*
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* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __HACKRF_HAL_H__
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#define __HACKRF_HAL_H__
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#include <cstdint>
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#include "adc.hpp"
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using namespace lpc43xx;
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namespace hackrf {
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namespace one {
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/* Clocks */
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using ClockFrequency = uint32_t;
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constexpr ClockFrequency si5351_xtal_f = 25000000U;
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constexpr ClockFrequency si5351_clkin_f = 10000000U;
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/* TODO: Use this many other places. */
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/* TODO: M4/M0 and peripheral rates may be more PortaPack-specific? Move out
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* of HackRF header? */
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constexpr ClockFrequency base_m4_clk_f = 200000000U;
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constexpr ClockFrequency base_m0_clk_f = base_m4_clk_f;
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constexpr ClockFrequency base_apb3_clk_f = base_m4_clk_f;
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constexpr ClockFrequency ssp1_pclk_f = base_m4_clk_f;
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constexpr ClockFrequency max5864_spi_f = 20000000U;
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constexpr ClockFrequency max283x_spi_f = 20000000U;
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constexpr ClockFrequency rffc5072_reference_f = 40000000U;
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constexpr ClockFrequency max283x_reference_f = 40000000U;
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constexpr ClockFrequency mcu_clkin_og_f = 40000000U;
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constexpr ClockFrequency mcu_clkin_r9_f = 10000000U;
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#ifdef PRALINE
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constexpr int8_t default_tx_gain_db = 16;
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#else
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constexpr int8_t default_tx_gain_db = 35;
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#endif
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constexpr uint8_t si5351_i2c_address = 0x60;
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/* Clock Generator */
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constexpr size_t clock_generator_output_og_codec = 0;
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constexpr size_t clock_generator_output_og_cpld = 1;
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constexpr size_t clock_generator_output_og_sgpio = 2;
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constexpr size_t clock_generator_output_og_clkout = 3;
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#ifdef PRALINE
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/* PRALINE has swapped CLK4/CLK5 vs HackRF One OG:
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* CLK4 = XCVR_CLK (MAX2831) = second IF
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* CLK5 = MIX_CLK (RFFC5072) = first IF */
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constexpr size_t clock_generator_output_og_first_if = 5; // RFFC5072 on CLK5
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constexpr size_t clock_generator_output_og_second_if = 4; // MAX2831 on CLK4
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#else
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constexpr size_t clock_generator_output_og_first_if = 4;
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constexpr size_t clock_generator_output_og_second_if = 5;
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#endif
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constexpr size_t clock_generator_output_og_mcu_clkin = 7;
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constexpr size_t clock_generator_output_r9_if = 0;
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constexpr size_t clock_generator_output_r9_sgpio = 1;
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constexpr size_t clock_generator_output_r9_clkout = 2;
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constexpr size_t clock_generator_output_r9_mcu_clkin = 2;
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/* ADC0 */
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using adc0 = adc::ADC<LPC_ADC0_BASE>;
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/* ADC1 */
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using adc1 = adc::ADC<LPC_ADC1_BASE>;
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} /* namespace one */
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} /* namespace hackrf */
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#endif /*__HACKRF_HAL_H__*/
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