mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-07-26 10:38:52 +00:00
Pezsma
9ab367f2e0
* Implement antenna bias control for Praline and update GPIO configurations * Add GPIO power management functions and update board initialization for Praline * Refactor power management functions for Praline and update GPIO configurations * Update GPIO configurations for Praline and enable power control pins. AA_EN enabled * Refactor GPIO configuration for Praline: update array size definitions and clean up comments * Add P1 and P2 control functions for PRALINE * Introduced P1_Function and P2_Function enums in ClockManager to manage multiplexer control. * mplemented set_p1_control and set_p2_control methods for configuring P1 and P2 control pins based on specified functions. * Updated clock_manager.hpp and clock_manager.cpp to include new functionality. * Modified MAX2837 and MAX2839 initialization to conditionally configure GPIO based on PRALINE. * Adjusted RFFC507x and RFFC507x_SPI initialization to include GPIO setup for PRALINE. - Refactored RF path initialization to remove unnecessary GPIO setup. - Updated board configuration for PRALINE to reflect new GPIO settings and pin configurations. - Cleaned up FPGA bridge code by removing unused pin configuration functions. - Adjusted SCU array size in pal_lld.h for PRALINE. - Enhanced hackrf_gpio.hpp to define multiplexer control pins for PRALINE. - Modified LED setup to accommodate active-low configuration for PRALINE. * Refactor GPIO and power control functions - Removed unused power control function declarations from board.h. - Enhanced gpio.hpp with new pin setup functions and GPIO control structures for PRALINE. - Consolidated multiplexer control pin definitions into gpio_control namespace. - Moved power control function implementations to gpio.cpp, including detailed VAA power management logic. - Updated power control functions to handle both PRALINE and HackRF R9 configurations. - Cleaned up hackrf_gpio.hpp by removing redundant multiplexer control definitions. * Refactor GPIO control for PRALINE: update MAX2831 and RFFC507x configurations, add new GPIO mappings * Refactor GPIO configurations for PRALINE: update anti-aliasing filter pin mapping, enhance LED setup logic, and add placeholder GPIO entries. * Refactor GPIO configurations for PRALINE: update LED mappings and remove unused anti-aliasing filter GPIO entry.
494 lines
12 KiB
C++
494 lines
12 KiB
C++
/*
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* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __PINS_H__
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#define __PINS_H__
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#include "gpio.hpp"
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namespace lpc43xx {
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enum Pins {
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P0_0,
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P0_1,
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P1_0,
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P1_1,
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P1_2,
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P1_3,
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P1_4,
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P1_5,
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P1_6,
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P1_7,
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P1_8,
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P1_9,
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P1_10,
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P1_11,
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P1_12,
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P1_13,
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P1_14,
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P1_15,
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P1_16,
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P1_17,
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P1_18,
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P1_19,
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P1_20,
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P2_0,
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P2_1,
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P2_2,
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P2_3,
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P2_4,
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P2_5,
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P2_6,
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P2_7,
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P2_8,
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P2_9,
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P2_10,
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P2_11,
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P2_12,
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P2_13,
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P3_0,
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P3_1,
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P3_2,
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P4_0,
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P4_1,
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P4_2,
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P4_3,
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P4_4,
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P4_5,
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P4_6,
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P4_7,
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P4_8,
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P4_9,
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P4_10,
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P5_0,
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P5_1,
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P5_2,
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P5_3,
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P5_4,
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P5_5,
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P5_6,
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P5_7,
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P6_0,
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P6_1,
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P6_2,
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P6_3,
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P6_4,
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P6_5,
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P6_6,
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P6_7,
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P6_8,
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P6_9,
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P6_10,
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P6_11,
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P6_12,
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P7_0,
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P7_1,
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P7_2,
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P7_3,
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P7_4,
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P7_5,
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P7_6,
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P7_7,
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P9_5,
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P9_6,
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#ifdef PRALINE
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P9_2,
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// Port A pins (PRALINE RF path control)
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PA_1,
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PA_2,
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// Port 8 pins (PRALINE power control and LED4)
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P8_1, // VAA_EN
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P8_4, // VBUS_IN_EN
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P8_5, // VIN_IN_EN
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P8_6,
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P8_7,
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// Port E pins (PRALINE transceiver control)
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PE_1,
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PE_2,
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PE_3,
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PE_4,
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// Port D pins (PRALINE - GPIO-only high-drive pins)
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// These use SCU_SFSPD registers, not normal SFSP
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// SCU configuration must be done separately in board.cpp
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PD_11,
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PD_12,
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PD_14,
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PD_15,
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PD_16,
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#endif
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PF_4,
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CLK0,
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CLK2,
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};
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constexpr Pin pins[]{
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[P0_0] = {0, 0},
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[P0_1] = {0, 1},
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[P1_0] = {1, 0},
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[P1_1] = {1, 1},
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[P1_2] = {1, 2},
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[P1_3] = {1, 3},
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[P1_4] = {1, 4},
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[P1_5] = {1, 5},
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[P1_6] = {1, 6},
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[P1_7] = {1, 7},
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[P1_8] = {1, 8},
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[P1_9] = {1, 9},
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[P1_10] = {1, 10},
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[P1_11] = {1, 11},
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[P1_12] = {1, 12},
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[P1_13] = {1, 13},
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[P1_14] = {1, 14},
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[P1_15] = {1, 15},
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[P1_16] = {1, 16},
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[P1_17] = {1, 17},
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[P1_18] = {1, 18},
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[P1_19] = {1, 19},
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[P1_20] = {1, 20},
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[P2_0] = {2, 0},
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[P2_1] = {2, 1},
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[P2_2] = {2, 2},
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[P2_3] = {2, 3},
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[P2_4] = {2, 4},
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[P2_5] = {2, 5},
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[P2_6] = {2, 6},
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[P2_7] = {2, 7},
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[P2_8] = {2, 8},
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[P2_9] = {2, 9},
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[P2_10] = {2, 10},
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[P2_11] = {2, 11},
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[P2_12] = {2, 12},
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[P2_13] = {2, 13},
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[P3_0] = {3, 0},
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[P3_1] = {3, 1},
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[P3_2] = {3, 2},
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[P4_0] = {4, 0},
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[P4_1] = {4, 1},
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[P4_2] = {4, 2},
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[P4_3] = {4, 3},
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[P4_4] = {4, 4},
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[P4_5] = {4, 5},
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[P4_6] = {4, 6},
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[P4_7] = {4, 7},
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[P4_8] = {4, 8},
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[P4_9] = {4, 9},
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[P4_10] = {4, 10},
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[P5_0] = {5, 0},
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[P5_1] = {5, 1},
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[P5_2] = {5, 2},
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[P5_3] = {5, 3},
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[P5_4] = {5, 4},
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[P5_5] = {5, 5},
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[P5_6] = {5, 6},
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[P5_7] = {5, 7},
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[P6_0] = {6, 0},
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[P6_1] = {6, 1},
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[P6_2] = {6, 2},
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[P6_3] = {6, 3},
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[P6_4] = {6, 4},
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[P6_5] = {6, 5},
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[P6_6] = {6, 6},
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[P6_7] = {6, 7},
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[P6_8] = {6, 8},
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[P6_9] = {6, 9},
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[P6_10] = {6, 10},
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[P6_11] = {6, 11},
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[P6_12] = {6, 12},
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[P7_0] = {7, 0},
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[P7_1] = {7, 1},
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[P7_2] = {7, 2},
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[P7_3] = {7, 3},
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[P7_4] = {7, 4},
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[P7_5] = {7, 5},
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[P7_6] = {7, 6},
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[P7_7] = {7, 7},
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[P9_5] = {9, 5},
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[P9_6] = {9, 6},
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#ifdef PRALINE
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[P9_2] = {9, 2},
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// Port A pins (function 0 = GPIO)
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[PA_1] = {0xA, 1},
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[PA_2] = {0xA, 2},
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// Port 8 pins
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[P8_1] = {8, 1},
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[P8_4] = {8, 4},
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[P8_5] = {8, 5},
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[P8_6] = {8, 6},
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[P8_7] = {8, 7},
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// Port E pins (function 4 = GPIO)
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[PE_1] = {0xE, 1},
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[PE_2] = {0xE, 2},
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[PE_3] = {0xE, 3},
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[PE_4] = {0xE, 4},
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// Port D pins - GPIO-only, no pin mux needed
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// Using 0xD as marker for Port D (SCU_SFSPD registers)
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[PD_11] = {0xD, 11},
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[PD_12] = {0xD, 12},
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[PD_14] = {0xD, 14},
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[PD_15] = {0xD, 15},
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[PD_16] = {0xD, 16},
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#endif
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[PF_4] = {15, 4},
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[CLK0] = {24, 0},
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[CLK2] = {24, 2},
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};
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enum GPIOs {
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GPIO0_0,
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GPIO0_1,
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GPIO0_2,
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GPIO0_3,
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GPIO0_4,
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GPIO0_5,
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/*GPIO0_6,*/
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GPIO0_7,
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GPIO0_8,
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GPIO0_9,
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GPIO0_10,
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GPIO0_11,
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GPIO0_12,
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GPIO0_13,
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GPIO0_14,
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GPIO0_15,
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GPIO1_0,
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GPIO1_1,
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GPIO1_2,
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GPIO1_3,
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GPIO1_4,
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GPIO1_5,
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GPIO1_6,
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GPIO1_7,
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GPIO1_8,
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GPIO1_9,
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GPIO1_10,
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GPIO1_11,
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GPIO1_12,
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GPIO1_13, /*GPIO1_14, GPIO1_15,*/
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GPIO2_0,
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GPIO2_1,
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GPIO2_2,
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GPIO2_3,
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GPIO2_4,
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GPIO2_5,
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GPIO2_6,
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GPIO2_7,
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GPIO2_8,
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GPIO2_9,
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GPIO2_10,
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GPIO2_11,
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GPIO2_12,
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GPIO2_13,
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GPIO2_14,
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GPIO2_15,
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GPIO3_0,
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GPIO3_1,
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GPIO3_2,
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GPIO3_3,
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GPIO3_4,
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GPIO3_5,
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GPIO3_6,
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GPIO3_7,
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GPIO3_8,
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GPIO3_9,
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GPIO3_10,
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GPIO3_11,
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GPIO3_12,
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GPIO3_13,
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GPIO3_14,
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GPIO3_15,
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GPIO4_11,
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GPIO5_0,
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GPIO5_1,
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GPIO5_2,
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GPIO5_3,
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GPIO5_4,
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GPIO5_5,
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GPIO5_6,
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GPIO5_7,
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GPIO5_8,
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GPIO5_9,
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/*GPIO5_10, GPIO5_11,*/
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GPIO5_12,
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GPIO5_13,
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GPIO5_14,
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GPIO5_15,
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GPIO5_16,
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GPIO5_18,
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// PRALINE-specific GPIOs (always defined to avoid compile-time array gaps)
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// RFFC5072 mixer data
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GPIO4_14,
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// Power control and LED4
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GPIO4_1,
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GPIO4_4, // VBUS_IN_EN
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GPIO4_5, // VIN_IN_EN
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GPIO4_6,
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GPIO4_7,
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// RF path control
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GPIO4_8,
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GPIO4_9,
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// Transceiver (MAX2831) control
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GPIO7_1,
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GPIO7_2,
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// Dual port control
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GPIO7_3,
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GPIO7_4,
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// GPIO6 (Port D pins)
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GPIO6_25,
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GPIO6_26,
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GPIO6_28,
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GPIO6_29,
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GPIO6_30,
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};
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constexpr GPIO gpio[] = {
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[GPIO0_0] = {pins[P0_0], 0, 0, 0},
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[GPIO0_1] = {pins[P0_1], 0, 1, 0},
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[GPIO0_2] = {pins[P1_15], 0, 2, 0},
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[GPIO0_3] = {pins[P1_16], 0, 3, 0},
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[GPIO0_4] = {pins[P1_0], 0, 4, 0},
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[GPIO0_5] = {pins[P6_6], 0, 5, 0},
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//[GPIO0_6] = { pins[P3_6], 0, 6, 0 },
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[GPIO0_7] = {pins[P2_7], 0, 7, 0},
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[GPIO0_8] = {pins[P1_1], 0, 8, 0},
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[GPIO0_9] = {pins[P1_2], 0, 9, 0},
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[GPIO0_10] = {pins[P1_3], 0, 10, 0},
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[GPIO0_11] = {pins[P1_4], 0, 11, 0},
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[GPIO0_12] = {pins[P1_17], 0, 12, 0},
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[GPIO0_13] = {pins[P1_18], 0, 13, 0},
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[GPIO0_14] = {pins[P2_10], 0, 14, 0},
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[GPIO0_15] = {pins[P1_20], 0, 15, 0},
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[GPIO1_0] = {pins[P1_7], 1, 0, 0},
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[GPIO1_1] = {pins[P1_8], 1, 1, 0},
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[GPIO1_2] = {pins[P1_9], 1, 2, 0},
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[GPIO1_3] = {pins[P1_10], 1, 3, 0},
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[GPIO1_4] = {pins[P1_11], 1, 4, 0},
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[GPIO1_5] = {pins[P1_12], 1, 5, 0},
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[GPIO1_6] = {pins[P1_13], 1, 6, 0},
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[GPIO1_7] = {pins[P1_14], 1, 7, 0},
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[GPIO1_8] = {pins[P1_5], 1, 8, 0},
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[GPIO1_9] = {pins[P1_6], 1, 9, 0},
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[GPIO1_10] = {pins[P2_9], 1, 10, 0},
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[GPIO1_11] = {pins[P2_11], 1, 11, 0},
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[GPIO1_12] = {pins[P2_12], 1, 12, 0},
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[GPIO1_13] = {pins[P2_13], 1, 13, 0},
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//[GPIO1_14] = { pins[P3_4], 1, 14, 0 },
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//[GPIO1_15] = { pins[P3_5], 1, 15, 0 },
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[GPIO2_0] = {pins[P4_0], 2, 0, 0},
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[GPIO2_1] = {pins[P4_1], 2, 1, 0},
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[GPIO2_2] = {pins[P4_2], 2, 2, 0},
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[GPIO2_3] = {pins[P4_3], 2, 3, 0},
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[GPIO2_4] = {pins[P4_4], 2, 4, 0},
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[GPIO2_5] = {pins[P4_5], 2, 5, 0},
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[GPIO2_6] = {pins[P4_6], 2, 6, 0},
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[GPIO2_7] = {pins[P5_7], 2, 7, 0},
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[GPIO2_8] = {pins[P6_12], 2, 8, 0},
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[GPIO2_9] = {pins[P5_0], 2, 9, 0},
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[GPIO2_10] = {pins[P5_1], 2, 10, 0},
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[GPIO2_11] = {pins[P5_2], 2, 11, 0},
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[GPIO2_12] = {pins[P5_3], 2, 12, 0},
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[GPIO2_13] = {pins[P5_4], 2, 13, 0},
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[GPIO2_14] = {pins[P5_5], 2, 14, 0},
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[GPIO2_15] = {pins[P5_6], 2, 15, 0},
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[GPIO3_0] = {pins[P6_1], 3, 0, 0},
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[GPIO3_1] = {pins[P6_2], 3, 1, 0},
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[GPIO3_2] = {pins[P6_3], 3, 2, 0},
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[GPIO3_3] = {pins[P6_4], 3, 3, 0},
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[GPIO3_4] = {pins[P6_5], 3, 4, 0},
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[GPIO3_5] = {pins[P6_9], 3, 5, 0},
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[GPIO3_6] = {pins[P6_10], 3, 6, 0},
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[GPIO3_7] = {pins[P6_11], 3, 7, 0},
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[GPIO3_8] = {pins[P7_0], 3, 8, 0},
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[GPIO3_9] = {pins[P7_1], 3, 9, 0},
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[GPIO3_10] = {pins[P7_2], 3, 10, 0},
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[GPIO3_11] = {pins[P7_3], 3, 11, 0},
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[GPIO3_12] = {pins[P7_4], 3, 12, 0},
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[GPIO3_13] = {pins[P7_5], 3, 13, 0},
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[GPIO3_14] = {pins[P7_6], 3, 14, 0},
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[GPIO3_15] = {pins[P7_7], 3, 15, 0},
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[GPIO4_11] = {pins[P9_6], 4, 11, 0},
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[GPIO5_0] = {pins[P2_0], 5, 0, 4},
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[GPIO5_1] = {pins[P2_1], 5, 1, 4},
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[GPIO5_2] = {pins[P2_2], 5, 2, 4},
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[GPIO5_3] = {pins[P2_3], 5, 3, 4},
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[GPIO5_4] = {pins[P2_4], 5, 4, 4},
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[GPIO5_5] = {pins[P2_5], 5, 5, 4},
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[GPIO5_6] = {pins[P2_6], 5, 6, 4},
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[GPIO5_7] = {pins[P2_8], 5, 7, 4},
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[GPIO5_8] = {pins[P3_1], 5, 8, 4},
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[GPIO5_9] = {pins[P3_2], 5, 9, 4},
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//[GPIO5_10] = { pins[P3_7], 5, 10, 4 },
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//[GPIO5_11] = { pins[P3_8], 5, 11, 4 },
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[GPIO5_12] = {pins[P4_8], 5, 12, 4},
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[GPIO5_13] = {pins[P4_9], 5, 13, 4},
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[GPIO5_14] = {pins[P4_10], 5, 14, 4},
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[GPIO5_15] = {pins[P6_7], 5, 15, 4},
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[GPIO5_16] = {pins[P6_8], 5, 16, 4},
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[GPIO5_18] = {pins[P9_5], 5, 18, 4},
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// PRALINE-specific GPIOs (use placeholder pins on non-PRALINE builds)
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#ifdef PRALINE
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[GPIO4_14] = {pins[P9_2], 4, 14, 0}, // RFFC5072 mixer data
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[GPIO4_1] = {pins[P8_1], 4, 1, 0}, // VAA disable
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[GPIO4_4] = {pins[P8_4], 4, 4, 0}, // VBUS_IN_EN
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[GPIO4_5] = {pins[P8_5], 4, 5, 0}, // VIN_IN_EN
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[GPIO4_6] = {pins[P8_6], 4, 6, 0}, // LED4
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[GPIO4_7] = {pins[P8_7], 4, 7, 0}, // 1V2 enable
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[GPIO4_8] = {pins[PA_1], 4, 8, 0}, // LPF enable
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[GPIO4_9] = {pins[PA_2], 4, 9, 0}, // RF amp enable
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[GPIO7_1] = {pins[PE_1], 7, 1, 4}, // MAX2831 enable
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[GPIO7_2] = {pins[PE_2], 7, 2, 4}, // MAX2831 RX enable
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[GPIO7_3] = {pins[PE_3], 7, 3, 4}, // P2 port control 0
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[GPIO7_4] = {pins[PE_4], 7, 4, 4}, // P2 port control 1
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[GPIO6_25] = {pins[PD_11], 6, 25, 4}, // Mixer lock detect
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[GPIO6_26] = {pins[PD_12], 6, 26, 4}, // Trigger input
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[GPIO6_28] = {pins[PD_14], 6, 28, 4}, // MAX283x chip select
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[GPIO6_29] = {pins[PD_15], 6, 29, 4}, // MAX2831 RXHP
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[GPIO6_30] = {pins[PD_16], 6, 30, 4}, // MAX5864 chip select
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#else
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// Placeholder entries for non-PRALINE builds (use P0_0 as dummy)
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[GPIO4_14] = {pins[P0_0], 4, 14, 0},
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[GPIO4_1] = {pins[P0_0], 4, 1, 0},
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[GPIO4_4] = {pins[P0_0], 4, 4, 0},
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[GPIO4_5] = {pins[P0_0], 4, 5, 0},
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[GPIO4_6] = {pins[P0_0], 4, 6, 0},
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[GPIO4_7] = {pins[P0_0], 4, 7, 0},
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[GPIO4_8] = {pins[P0_0], 4, 8, 0},
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[GPIO4_9] = {pins[P0_0], 4, 9, 0},
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[GPIO7_1] = {pins[P0_0], 7, 1, 0},
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[GPIO7_2] = {pins[P0_0], 7, 2, 0},
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[GPIO7_3] = {pins[P0_0], 7, 3, 0},
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[GPIO7_4] = {pins[P0_0], 7, 4, 0},
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[GPIO6_25] = {pins[P0_0], 6, 25, 0},
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[GPIO6_26] = {pins[P0_0], 6, 26, 0},
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[GPIO6_28] = {pins[P0_0], 6, 28, 0},
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[GPIO6_29] = {pins[P0_0], 6, 29, 0},
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[GPIO6_30] = {pins[P0_0], 6, 30, 0},
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#endif
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};
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} // namespace lpc43xx
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#endif /*__PINS_H__*/
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