mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-08-26 17:39:21 +00:00
Bernd Herzog
47c94dbf26
* enabled sd over usb compilation * updated hackrf pro usb stack * fixed hackrf one code path * fixed hackrf pro code path * improved performance * fixed sd card clock * refactoring * formatted code
264 lines
9.2 KiB
C
264 lines
9.2 KiB
C
/*
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* Copyright 2026 Great Scott Gadgets <info@greatscottgadgets.com>
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "cpu_clock.h"
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#include <stdint.h>
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#include <libopencm3/lpc43xx/cgu.h>
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#if defined(IS_JAWBREAKER) || defined(IS_HACKRF_ONE) || defined(IS_PRALINE)
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#include <libopencm3/lpc43xx/ccu.h>
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#endif
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#include "delay.h"
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#include "i2c_bus.h"
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#include "i2c_lpc.h"
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#include "si5351c.h"
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/* We start with the CPU clock at 96MHz */
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unsigned int cpu_clock_mhz = 96;
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/*
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Configure PLL1 (Main MCU Clock) to max speed (204MHz).
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Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
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This function shall be called after cpu_clock_init().
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*/
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static void cpu_clock_pll1_max_speed(void) {
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uint32_t reg_val;
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/* This function implements the sequence recommended in:
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* UM10503 Rev 2.4 (Aug 2018), section 13.2.1.1, page 167. */
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/* 1. Select the IRC as BASE_M4_CLK source. */
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reg_val = CGU_BASE_M4_CLK;
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reg_val &= ~CGU_BASE_M4_CLK_CLK_SEL_MASK;
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reg_val |= CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_IRC) | CGU_BASE_M4_CLK_AUTOBLOCK(1);
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CGU_BASE_M4_CLK = reg_val;
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/* CPU is now at 12MHz */
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cpu_clock_mhz = 12;
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/* 2. Enable the crystal oscillator. */
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CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE_MASK;
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/* 3. Wait 250us. */
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delay_us(250);
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/* 4. Set the AUTOBLOCK bit. */
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CGU_PLL1_CTRL |= CGU_PLL1_CTRL_AUTOBLOCK(1);
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/* 5. Reconfigure PLL1 to produce the final output frequency, with the
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* crystal oscillator as clock source. */
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reg_val = CGU_PLL1_CTRL;
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// clang-format off
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reg_val &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK |
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CGU_PLL1_CTRL_PD_MASK |
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CGU_PLL1_CTRL_FBSEL_MASK |
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CGU_PLL1_CTRL_BYPASS_MASK |
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CGU_PLL1_CTRL_DIRECT_MASK |
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CGU_PLL1_CTRL_PSEL_MASK |
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CGU_PLL1_CTRL_MSEL_MASK |
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CGU_PLL1_CTRL_NSEL_MASK );
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/* Set PLL1 up to 12MHz * 17 = 204MHz.
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* Direct mode: FCLKOUT = FCCO = M*(FCLKIN/N) */
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reg_val |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL) |
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CGU_PLL1_CTRL_PSEL(0) |
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CGU_PLL1_CTRL_NSEL(0) |
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CGU_PLL1_CTRL_MSEL(16) |
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CGU_PLL1_CTRL_FBSEL(0) |
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CGU_PLL1_CTRL_DIRECT(1);
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// clang-format on
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CGU_PLL1_CTRL = reg_val;
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/* 6. Wait for PLL1 to lock. */
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while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK)) {
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}
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/* 7. Set the PLL1 P-divider to divide by 2 (DIRECT=0, PSEL=0). */
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CGU_PLL1_CTRL &= ~CGU_PLL1_CTRL_DIRECT_MASK;
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/* 8. Select PLL1 as BASE_M4_CLK source. */
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reg_val = CGU_BASE_M4_CLK;
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reg_val &= ~CGU_BASE_M4_CLK_CLK_SEL_MASK;
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reg_val |= CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1);
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CGU_BASE_M4_CLK = reg_val;
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/* CPU is now at 102MHz */
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cpu_clock_mhz = 102;
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/* 9. Wait 50us. */
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delay_us(50);
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/* 10. Set the PLL1 P-divider to direct output mode (DIRECT=1). */
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CGU_PLL1_CTRL |= CGU_PLL1_CTRL_DIRECT_MASK;
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/* CPU is now at 204MHz */
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cpu_clock_mhz = 204;
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}
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/* clock startup for LPC4320 configure PLL1 to max speed (204MHz).
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Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */
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void cpu_clock_init(void) {
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/* use IRC as clock source for APB1 (including I2C0) */
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CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);
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/* use IRC as clock source for APB3 */
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CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC);
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// FIXME disable I2C
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/* Kick I2C0 down to 400kHz when we switch over to APB1 clock = 204MHz */
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i2c_bus_start(si5351c.bus, &i2c_config_fast_clock);
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/*
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* 12MHz clock is entering LPC XTAL1/OSC input now.
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* On HackRF One and Jawbreaker, there is a 12 MHz crystal at the LPC.
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* Set up PLL1 to run from XTAL1 input.
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*/
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// FIXME a lot of the details here should be in a CGU driver
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/* set xtal oscillator to low frequency mode */
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CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF_MASK;
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cpu_clock_pll1_max_speed();
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/* use XTAL_OSC as clock source for APB1 */
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CGU_BASE_APB1_CLK =
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CGU_BASE_APB1_CLK_AUTOBLOCK(1) | CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
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/* use XTAL_OSC as clock source for APB3 */
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CGU_BASE_APB3_CLK =
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CGU_BASE_APB3_CLK_AUTOBLOCK(1) | CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);
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/* use XTAL_OSC as clock source for PLL0USB */
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CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1) | CGU_PLL0USB_CTRL_AUTOBLOCK(1) |
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CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL);
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while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK) {
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}
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/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
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/* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */
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CGU_PLL0USB_MDIV = 0x06167FFA;
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CGU_PLL0USB_NP_DIV = 0x00302062;
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CGU_PLL0USB_CTRL |=
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(CGU_PLL0USB_CTRL_PD(1) | CGU_PLL0USB_CTRL_DIRECTI(1) |
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CGU_PLL0USB_CTRL_DIRECTO(1) | CGU_PLL0USB_CTRL_CLKEN(1));
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/* power on PLL0USB and wait until stable */
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CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD_MASK;
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while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK)) {
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}
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/* use PLL0USB as clock source for USB0 */
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CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK(1) |
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CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);
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/* Switch peripheral clock over to use PLL1 (204MHz) */
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CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK(1) |
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CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
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/* Switch APB1 clock over to use PLL1 (204MHz) */
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CGU_BASE_APB1_CLK =
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CGU_BASE_APB1_CLK_AUTOBLOCK(1) | CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
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/* Switch APB3 clock over to use PLL1 (204MHz) */
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CGU_BASE_APB3_CLK =
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CGU_BASE_APB3_CLK_AUTOBLOCK(1) | CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1);
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CGU_BASE_SSP0_CLK =
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CGU_BASE_SSP0_CLK_AUTOBLOCK(1) | CGU_BASE_SSP0_CLK_CLK_SEL(CGU_SRC_PLL1);
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CGU_BASE_SSP1_CLK =
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CGU_BASE_SSP1_CLK_AUTOBLOCK(1) | CGU_BASE_SSP1_CLK_CLK_SEL(CGU_SRC_PLL1);
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#ifdef IS_NOT_RAD1O
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if (IS_NOT_RAD1O) {
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/* Disable unused clocks */
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/* Start with PLLs */
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CGU_PLL0AUDIO_CTRL = CGU_PLL0AUDIO_CTRL_PD(1);
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/* Dividers */
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CGU_IDIVA_CTRL = CGU_IDIVA_CTRL_PD(1);
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CGU_IDIVB_CTRL = CGU_IDIVB_CTRL_PD(1);
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CGU_IDIVC_CTRL = CGU_IDIVC_CTRL_PD(1);
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CGU_IDIVD_CTRL = CGU_IDIVD_CTRL_PD(1);
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CGU_IDIVE_CTRL = CGU_IDIVE_CTRL_PD(1);
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/* Base clocks */
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CGU_BASE_SPIFI_CLK =
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CGU_BASE_SPIFI_CLK_PD(1); /* SPIFI is only used at boot */
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CGU_BASE_USB1_CLK =
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CGU_BASE_USB1_CLK_PD(1); /* USB1 is not exposed on HackRF */
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CGU_BASE_PHY_RX_CLK = CGU_BASE_PHY_RX_CLK_PD(1);
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CGU_BASE_PHY_TX_CLK = CGU_BASE_PHY_TX_CLK_PD(1);
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CGU_BASE_LCD_CLK = CGU_BASE_LCD_CLK_PD(1);
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CGU_BASE_VADC_CLK = CGU_BASE_VADC_CLK_PD(1);
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CGU_BASE_SDIO_CLK = CGU_BASE_SDIO_CLK_PD(0) | CGU_BASE_SDIO_CLK_AUTOBLOCK(1) | CGU_BASE_SDIO_CLK_CLK_SEL(0x09);
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CGU_BASE_UART0_CLK = CGU_BASE_UART0_CLK_PD(1);
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CGU_BASE_UART1_CLK = CGU_BASE_UART1_CLK_PD(1);
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CGU_BASE_UART2_CLK = CGU_BASE_UART2_CLK_PD(1);
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CGU_BASE_UART3_CLK = CGU_BASE_UART3_CLK_PD(1);
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CGU_BASE_OUT_CLK = CGU_BASE_OUT_CLK_PD(1);
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CGU_BASE_AUDIO_CLK = CGU_BASE_AUDIO_CLK_PD(1);
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CGU_BASE_CGU_OUT0_CLK = CGU_BASE_CGU_OUT0_CLK_PD(1);
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CGU_BASE_CGU_OUT1_CLK = CGU_BASE_CGU_OUT1_CLK_PD(1);
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/* Disable unused peripheral clocks */
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CCU1_CLK_APB1_CAN1_CFG = 0;
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CCU1_CLK_APB1_I2S_CFG = 0;
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CCU1_CLK_APB1_MOTOCONPWM_CFG = 0;
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// CCU1_CLK_APB3_ADC0_CFG = 0;
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CCU1_CLK_APB3_ADC1_CFG = 0;
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CCU1_CLK_APB3_CAN0_CFG = 0;
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CCU1_CLK_APB3_DAC_CFG = 0;
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// CCU1_CLK_M4_DMA_CFG = 0;
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CCU1_CLK_M4_EMC_CFG = 0;
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CCU1_CLK_M4_EMCDIV_CFG = 0;
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CCU1_CLK_M4_ETHERNET_CFG = 0;
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CCU1_CLK_M4_LCD_CFG = 0;
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CCU1_CLK_M4_QEI_CFG = 0;
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CCU1_CLK_M4_RITIMER_CFG = 0;
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// CCU1_CLK_M4_SCT_CFG = 0;
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// CCU1_CLK_M4_SDIO_CFG = 1;
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CCU1_CLK_M4_SPIFI_CFG = 0;
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CCU1_CLK_M4_TIMER0_CFG = 0;
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// CCU1_CLK_M4_TIMER1_CFG = 0;
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// CCU1_CLK_M4_TIMER2_CFG = 0;
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CCU1_CLK_M4_TIMER3_CFG = 0;
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CCU1_CLK_M4_UART1_CFG = 0;
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CCU1_CLK_M4_USART0_CFG = 0;
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CCU1_CLK_M4_USART2_CFG = 0;
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CCU1_CLK_M4_USART3_CFG = 0;
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CCU1_CLK_M4_USB1_CFG = 0;
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CCU1_CLK_M4_VADC_CFG = 0;
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// CCU1_CLK_SPIFI_CFG = 0;
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// CCU1_CLK_USB1_CFG = 0;
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// CCU1_CLK_VADC_CFG = 0;
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// CCU2_CLK_APB0_UART1_CFG = 0;
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// CCU2_CLK_APB0_USART0_CFG = 0;
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// CCU2_CLK_APB2_USART2_CFG = 0;
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// CCU2_CLK_APB2_USART3_CFG = 0;
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// CCU2_CLK_APLL_CFG = 0;
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// CCU2_CLK_SDIO_CFG = 0;
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}
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#endif
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}
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